# US 12,764,938 B2 · Memory device and manufacturing method thereof

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- Number: US 12,764,938 B2
- Document ID: US12764938B2
- Status: Granted
- Kind: B2
- Application number: 18/571,781
- Filed: 2023-11-10
- Published: 2025-03-13
- Granted: 2026-10-13
- Earliest claimed: 2022-12-21
- Assignees: Seoul National University R&Db Foundation
- Applicants: Seoul National University R&DB foundation
- Inventors: Cheol Seong Hwang
- Web page: https://patentgrep.com/patent/US12764938B2

## CPC

- H10B 12/37: {the capacitor being at least partially in a trench in the substrate}
- H10B 12/0387: {Making the trench}
- H10B 12/488: {Word lines}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure discloses a manufacturing method including forming a stack including a first insulating layer, and a first sacrificial layer and a second insulating layer which are sequentially stacked on the first insulating layer; forming a patterned stack including at least one pattern portion having a first sacrificial layer obtained from the first sacrificial layer by patterning the stack; forming a structure including the patterned stack and the insulating material by filling empty spaces on both sides of the at least one pattern portion with an insulating material; forming a first vertical hole penetrating through the first sacrificial layer pattern of the pattern portion in the structure; forming a horizontal hole by removing the first sacrificial layer pattern exposed by the first vertical hole; and forming a gate insulating material layer on inner surfaces of the first vertical hole and the horizontal hole.

## Claims

### Claim 1

A manufacturing method of a memory device comprising:
forming a stack including a first insulating layer, and a first sacrificial layer and a second insulating layer which are sequentially stacked on the first insulating layer;
forming a patterned stack having at least one pattern portion having a first sacrificial layer pattern obtained from the first sacrificial layer by patterning the stack, wherein the pattern portion has a shape extending in a first direction, and empty spaces are provided on both sides of the pattern portion along a second direction perpendicular to the first direction;
forming a structure including the patterned stack and an insulating material by filling the empty spaces on both sides of the at least one pattern portion with the insulating material;
forming a first vertical hole penetrating through the first sacrificial layer pattern of the pattern portion in the structure;
forming a horizontal hole extending in the first direction by removing the first sacrificial layer pattern exposed by the first vertical hole;
forming a gate insulating material layer on inner surfaces of the first vertical hole and the horizontal hole, and forming a channel material layer filling the first vertical hole and the horizontal hole on the gate insulating material layer;
forming a second vertical hole in a region corresponding to the first vertical hole in the structure where the gate insulating material layer and the channel material layer are formed;
exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material from a transistor formation region around the second vertical hole of the structure;
defining a transistor including a word line by forming the word line surrounding the exposed portion of the gate insulating material layer in the transistor formation region;
forming a first trench in a capacitor formation region adjacent to the transistor formation region of the structure;
forming a first recess exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material exposed by the first trench in the capacitor formation region;
forming a mold insulating layer filling the first recess;
forming a bit line connected to one end of the channel material layer in a region corresponding to the second vertical hole in the transistor formation region; and
forming a second recess by removing the channel material layer and the gate insulating material layer from the capacitor formation region, forming an electrode member connected to the other end of the channel material layer on an inner surface of the second recess, and forming a capacitor including the electrode member, a dielectric layer, and a plate electrode by sequentially forming the dielectric layer and the plate electrode on the electrode member.

### Claim 2 (depends on 1)

The manufacturing method of a memory device of claim 1, wherein the entire first sacrificial layer pattern is removed in the forming the horizontal hole.

### Claim 3 (depends on 1)

The manufacturing method of a memory device of claim 1, wherein the first insulating layer, the second insulating layer, and the insulating material include a silicon nitride, and the first sacrificial layer includes a silicon oxide.

### Claim 4 (depends on 1)

The manufacturing method of a memory device of claim 1, wherein the channel material layer includes an oxide semiconductor.

### Claim 5 (depends on 1)

The manufacturing method of a memory device of claim 1, wherein the defining the transistor by forming the word line includes:
forming a word line material layer surrounding the exposed portion of the gate insulating material layer in the transistor formation region;
forming a through hole by etching a region corresponding to the second vertical hole in the word line material layer;
recessing a portion of the word line material layer exposed through the through hole so that the one end of the channel material layer protrudes toward the through hole rather than the word line material layer; and
forming a body insulating layer to fill the through hole.

### Claim 6 (depends on 5)

The manufacturing method of a memory device of claim 5, further comprising recessing a portion of the word line material layer exposed by the first recess after forming the first recess in the capacitor formation region.

### Claim 7 (depends on 5)

The manufacturing method of a memory device of claim 5, wherein the forming the bit line includes:
forming a third vertical hole in a region of the body insulating layer corresponding to the second vertical hole; and
forming the bit line in the third vertical hole.

### Claim 8 (depends on 1)

The manufacturing method of a memory device of claim 1, further comprising:
forming an insertion insulating layer surrounding the exposed gate insulating material layer in the capacitor formation region after forming the first recess in the capacitor formation region, wherein the mold insulating layer is formed to fill the first recess and the first trench on the insertion insulating layer; and
forming a second trench in a region corresponding to the first trench in the mold insulating layer is further included, wherein the second recess is formed by etching the channel material layer, the gate insulating material layer, and the insertion insulating layer exposed by the second trench.

### Claim 9 (depends on 1)

The manufacturing method of a memory device of claim 1, further comprising exposing an outer surface of the electrode member by etching the mold insulating layer after forming the electrode member, wherein the dielectric layer and the plate electrode are sequentially formed after etching the mold insulating layer.

### Claim 10 (depends on 1)

The manufacturing method of a memory device of claim 1, wherein the stack further includes a second sacrificial layer and a third insulating layer sequentially stacked on the second insulating layer, and the stack has a vertically symmetrical structure with respect to the second insulating layer.

### Claim 11 (depends on 10)

The manufacturing method of a memory device of claim 10, wherein the second insulating layer has a thickness larger than that of each of the first insulating layer, the third insulating layer, the first sacrificial layer, and the second sacrificial layer.

### Claim 12 (depends on 10)

The manufacturing method of a memory device of claim 10, wherein the transistor is a first transistor, the capacitor is a first capacitor, and the memory device further includes a second transistor disposed on the first transistor and a second capacitor disposed on the first capacitor.

### Claim 13

A manufacturing method of a memory device comprising:
forming a stack including a first insulating layer, and a first sacrificial layer and a second insulating layer which are sequentially stacked on the first insulating layer;
forming a patterned stack having at least one pattern portion having a first sacrificial layer pattern obtained from the first sacrificial layer by patterning the stack, wherein the pattern portion has a shape extending in a first direction, and empty spaces are provided on both sides of the pattern portion along a second direction perpendicular to the first direction;
forming a structure including the patterned stack and an insulating material by filling the empty spaces on both sides of the at least one pattern portion with the insulating material;
forming a first vertical hole penetrating through the first sacrificial layer pattern of the pattern portion in the structure;
forming a horizontal hole extending in the first direction by removing the first sacrificial layer pattern exposed by the first vertical hole;
forming a gate insulating material layer on inner surfaces of the first vertical hole and the horizontal hole, and forming a dummy channel material layer to fill the first vertical hole and the horizontal hole on the gate insulating material layer;
forming a second vertical hole in a region corresponding to the first vertical hole in the structure where the gate insulating material layer and the dummy channel material layer are formed;
exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material from a transistor formation region around the second vertical hole of the structure;
forming a word line surrounding the exposed portion of the gate insulating material layer in the transistor formation region;
forming a first trench in a capacitor formation region adjacent to the transistor formation region of the structure;
forming a first recess exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material exposed by the first trench in the capacitor formation region;
forming a mold insulating layer filling the first recess;
forming a second recess by removing the dummy channel material layer and the gate insulating material layer from the capacitor formation region, forming an electrode member on an inner surface of the second recess, forming a capacitor including the electrode member, a dielectric layer, and a plate electrode by sequentially forming the dielectric layer and the plate electrode on the electrode member;
forming an empty channel space by removing the dummy channel material layer from the transistor formation region, and forming a channel material layer connected to the capacitor in the empty channel space to define a transistor including the channel material layer; and
forming a bit line connected to the channel material layer.

### Claim 14 (depends on 13)

The manufacturing method of a memory device of claim 13, wherein the first insulating layer, the second insulating layer, and the insulating material include a silicon nitride, and the first sacrificial layer includes a silicon oxide.

### Claim 15 (depends on 13)

The manufacturing method of a memory device of claim 13, wherein the dummy channel material layer includes poly-silicon (poly-Si).

### Claim 16 (depends on 13)

The manufacturing method of a memory device of claim 13, wherein the channel material layer includes an oxide semiconductor.

### Claim 17 (depends on 13)

The manufacturing method of a memory device of claim 13, wherein the forming the word line includes:
forming a word line material layer surrounding the exposed portion of the gate insulating material layer in the transistor formation region;
forming a through hole by etching a region corresponding to the second vertical hole in the word line material layer;
recessing a portion of the word line material layer exposed through the through hole so that one end of the dummy channel material layer protrudes toward the through hole rather than the word line material layer; and
forming a body insulating layer to fill the through hole.

### Claim 18 (depends on 17)

The manufacturing method of a memory device of claim 17, further comprising recessing a portion of the word line material layer exposed by the first recess after forming the first recess in the capacitor formation region.

### Claim 19 (depends on 17)

The manufacturing method of a memory device of claim 17, wherein the forming the empty channel space and forming the channel material layer include:
forming a third vertical hole in a region of the body insulating layer corresponding to the second vertical hole;
forming the empty channel space by removing the dummy channel material layer exposed by the third vertical hole; and
forming the channel material layer in the empty channel space and the third vertical hole.

### Claim 20 (depends on 19)

The manufacturing method of a memory device of claim 19, wherein the forming the bit line includes:
reforming the third vertical hole by removing a portion of the channel material layer formed in the third vertical hole; and
forming the bit line in the reformed third vertical hole.

### Claim 21 (depends on 13)

The manufacturing method of a memory device of claim 13, further comprising:
forming an insertion insulating layer surrounding the exposed portion of the gate insulating material layer in the capacitor formation region after forming the first recess in the capacitor formation region, wherein the mold insulating layer is formed to fill the first recess and the first trench on the insertion insulating layer; and
forming a second trench in a region corresponding to the first trench in the mold insulating layer is further included, wherein the second recess is formed by etching the dummy channel material layer, the gate insulating material layer, and the insertion insulating layer exposed by the second trench.

### Claim 22 (depends on 13)

The manufacturing method of a memory device of claim 13, further comprising etching the mold insulating layer to expose an outer surface of the electrode member after forming the electrode member, wherein the dielectric layer and the plate electrode are sequentially formed after etching the mold insulating layer.

### Claim 23 (depends on 13)

The manufacturing method of a memory device of claim 13,
wherein the stack further includes a second sacrificial layer and a third insulating layer sequentially stacked on the second insulating layer,
wherein the stack has a vertically symmetrical structure with respect to the second insulating layer.

### Claim 24 (depends on 23)

The manufacturing method of a memory device of claim 23, wherein the second insulating layer has a thickness larger than that of each of the first insulating layer, the third insulating layer, the first sacrificial layer, and the second sacrificial layer.

### Claim 25 (depends on 23)

The manufacturing method of a memory device of claim 23, wherein the transistor is a first transistor, the capacitor is a first capacitor, and the memory device further includes a second transistor disposed on the first transistor and a second capacitor disposed on the first capacitor.