Memory cell with reduced parasitic capacitance and method of manufacturing the same

A method of manufacturing a memory device, comprising:

• providing a substrate including an upper surface;
• performing a first etching operation to form a first trench in the substrate;
• depositing a first dielectric layer on sidewalls of the first trench;
• forming a first gate electrode in the first trench and laterally surrounded by the first dielectric layer;
• depositing a second dielectric layer and forming a low-k layer in the first trench over the first gate electrode, wherein the low-k layer includes a dielectric constant less than that of the first dielectric layer and the second dielectric layer;
• depositing a capping layer over the first gate electrode to fill the first trench;
• depositing a third dielectric layer to cover the low-k layer;
• and
• etching an upper portion of the first dielectric layer to form a second trench, wherein the second dielectric layer and the low-k layer are formed in the second trench;
• wherein the depositing of the capping layer is performed prior to the depositing of the second dielectric layer.