# US 12,764,935 B2 · Transistor, manufacturing method thereof, and memory

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- Number: US 12,764,935 B2
- Document ID: US12764935B2
- Status: Granted
- Kind: B2
- Application number: 18/151,434
- Filed: 2023-01-07
- Published: 2023-11-30
- Granted: 2026-10-13
- Earliest claimed: 2022-05-26
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Chun-Wei Liao; Xiaoguang Wang; Deyuan Xiao; Tzung-Han Lee
- Web page: https://patentgrep.com/patent/US12764935B2

## CPC

- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.

## Claims

### Claim 1

A transistor, comprising:
a substrate comprising an active area;
a gate structure penetrating through the active area and comprising a gate and a gate dielectric layer, the gate dielectric layer covering sidewalls and a bottom of the gate;
a channel layer located on a side of the gate dielectric layer away from the gate, the channel layer comprising a metal oxide semiconductor layer;
wherein the active area comprises a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer;
wherein the first active layer and the second active layer are located on a top of the channel layer, and
the gate dielectric layer covers sidewalls of the first active layer and the second active layer, and part of the top of the channel layer not covered by the first active layer and the second active layer.

### Claim 2 (depends on 1)

The transistor according to claim 1, wherein a material of the metal oxide semiconductor layer comprises at least one of indium gallium zinc oxide, indium tin oxide, indium tungsten oxide, indium zinc oxide, gallium oxide or indium oxide.

### Claim 3 (depends on 1)

The transistor according to claim 1, wherein a thickness of the metal oxide semiconductor layer is 0.5 nm to 3 nm.

### Claim 4 (depends on 1)

The transistor according to claim 1, wherein the channel layer comprises at least one sub-channel layer group, and the sub-channel layer group comprises two sub-channel layers stacked in sequence, and one of the two sub-channel layers comprises the metal oxide semiconductor layer and another of the two sub-channel layers comprises a silicon germanium semiconductor layer or a silicon semiconductor layer.

### Claim 5 (depends on 1)

The transistor according to claim 1, wherein the metal oxide semiconductor layer covers sidewalls of the first active layer and the second active layer close to the gate structure.

### Claim 6 (depends on 1)

The transistor according to claim 1, wherein the gate comprises a first portion and a second portion, and the first portion is located on a side of the second portion close to a surface of the substrate, and the first portion has a first dimension along a given direction, and the second portion has a second dimension along the given direction, and the first dimension is greater than the second dimension, and the given direction is parallel to the surface of the substrate and perpendicular to an extending direction of the gate.

### Claim 7 (depends on 1)

The transistor according to claim 1, wherein the gate comprises a first sub-gate and a second sub-gate, and the second sub-gate is located on a side of the first sub-gate close to a surface of the substrate, and a material of the first sub-gate comprises a metal, and a material of the second sub-gate comprises polysilicon.

### Claim 8 (depends on 7)

The transistor according to claim 7, wherein a top of a cross section of the first sub-gate is Q-shaped.

### Claim 9 (depends on 7)

The transistor according to claim 7, wherein a third dimension of the second sub-gate is equal to a first dimension of a first portion of the first sub-gate and greater than a second dimension of a second portion, the first portion is located on a side of the second portion close to the surface of the substrate, and the first dimension, the second dimension and the third dimension are along a direction parallel to the surface of the substrate and perpendicular to an extending direction of the gate.

### Claim 10 (depends on 7)

The transistor according to claim 7, wherein a cross section of the first sub-gate is T-shaped.

### Claim 11 (depends on 1)

A memory comprising a storage unit, wherein the storage unit is configured to store data and comprises the transistor according to claim 1.

### Claim 12 (depends on 11)

The memory according to claim 11, wherein the storage unit further comprises:
a capacitor coupled to the first active layer or the second active layer of the transistor in the storage unit.

### Claim 13

A method for manufacturing a transistor, comprising:
providing a substrate, wherein the substrate comprises an active area, and a trench penetrating through the active area is provided in the substrate;
forming a first active layer and a second active layer in the active area, wherein the first active layer and the second active layer are respectively arranged at two sides of the trench;
forming a channel layer on a bottom and sidewalls of the trench located at the active area, wherein the channel layer comprises a metal oxide semiconductor layer and is in contact with the first active layer and the second active layer; and
forming a gate dielectric layer and a gate in sequence in the trench, wherein the gate dielectric layer covers the channel layer;
wherein the channel layer comprises a first sub-channel layer and a second sub-channel layer stacked in sequence; and the forming the channel layer on the bottom and sidewalls of the trench located at the active area comprises:
implanting doping ions into the bottom and the sidewalls of the trench located at the active area to form the first sub-channel layer; and
forming the second sub-channel layer covering a bottom and sidewalls of the first sub-channel layer, wherein the second sub-channel layer comprises the metal oxide semiconductor layer;
wherein the first active layer and the second active layer are located on a top of the first sub-channel layer, and a top of the second sub-channel layer and a top of the first sub-channel layer are flush, and
wherein the forming the gate dielectric layer in the trench comprises:
forming the gate dielectric layer in the trench, wherein the gate dielectric layer covers the top of the second sub-channel layer and sidewalls of the first active layer and the second active layer.

### Claim 14 (depends on 13)

The method according to claim 13, wherein a material of the metal oxide semiconductor layer comprises at least one of indium gallium zinc oxide, indium tin oxide, indium tungsten oxide, indium zinc oxide, gallium oxide or indium oxide.

### Claim 15 (depends on 13)

The method according to claim 13, wherein a thickness of the metal oxide semiconductor layer is 0.5 nm to 3 nm.

### Claim 16 (depends on 13)

The method according to claim 13, wherein the first active layer and the second active layer are located on a top of the first sub-channel layer, and the second sub-channel layer also covers sidewalls of the first active layer and the second active layer close to the gate; and the forming the second sub-channel layer covering the bottom and sidewalls of the first sub-channel layer comprises:
forming the second sub-channel layer covering the bottom and the sidewalls of the trench; wherein a top of the second sub-channel layer, a top of the first active layer and a top of the second active layer are flush.

### Claim 17 (depends on 13)

The method according to claim 13, wherein the first active layer and the second active layer are located on a top of the first sub-channel layer, and a top of the second sub-channel layer and a top of the first sub-channel layer are flush, and
wherein the forming the gate dielectric layer in the trench comprises:
forming the gate dielectric layer in the trench, wherein the gate dielectric layer covers the top of the second sub-channel layer and sidewalls of the first active layer and the second active layer.

### Claim 18 (depends on 13)

The method according to claim 13, wherein the gate comprises a first sub-gate and a second sub-gate, and the second sub-gate is located on a side of the first sub-gate close to a surface of the substrate, and
wherein the forming the gate in the trench comprises:
forming the first sub-gate on a side of the gate dielectric layer away from the channel layer, wherein a material of the first sub-gate comprises a metal; and
forming the second sub-gate on a top of the first sub-gate; wherein a material of the second sub-gate comprises polysilicon.