# US 12,764,934 B2 · Memory cell with reduced parasitic capacitance

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- Number: US 12,764,934 B2
- Document ID: US12764934B2
- Status: Granted
- Kind: B2
- Application number: 18/127,774
- Filed: 2023-03-29
- Published: 2024-10-03
- Granted: 2026-10-13
- Earliest claimed: 2023-03-29
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Kai-Po Shang
- Web page: https://patentgrep.com/patent/US12764934B2

## CPC

- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/46: comprising air gaps
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/488: {Word lines}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a memory device and a method of manufacturing the same. The memory device includes a substrate; a first gate electrode arranged within the substrate; a second gate electrode arranged within the substrate and over the first gate electrode; and a gate dielectric layer separating the substrate from the first gate electrode and the second gate electrode from the substrate. The gate dielectric layer includes: a first dielectric layer arranged within the substrate and laterally surrounding the first gate electrode; a second dielectric layer over the first dielectric layer and laterally surrounding the second gate electrode; and a low-k layer arranged over the first dielectric layer and laterally surrounded by the second dielectric layer, wherein the low-k layer has a dielectric constant less than that of the first dielectric layer or the second dielectric layer.

## Claims

### Claim 1

A memory device, comprising:
a substrate;
a first gate electrode arranged within the substrate;
a second gate electrode arranged within the substrate and in direct contact with the first gate electrode;
a gate dielectric layer separating the substrate from the first gate electrode and the second gate electrode from the substrate, wherein the gate dielectric layer comprises:
a first dielectric layer arranged within the substrate and laterally surrounding the first gate electrode;
a second dielectric layer over the first dielectric layer and laterally surrounding the second gate electrode;
a capping layer disposed on and in direct contact with the second gate electrode;
a low-k layer arranged over the first dielectric layer and laterally surrounded by the second dielectric layer, wherein the low-k layer has a dielectric constant less than that of the first dielectric layer or the second dielectric layer;
a third dielectric layer disposed on and in direct contact with an upper surface of the second dielectric layer, an upper surface of the capping layer, and an upper surface of the low-k layer; and
a barrier layer laterally surrounding the first gate electrode and laterally surrounded by the low-k layer and the second dielectric layer, wherein the barrier layer is formed between the low-k layer and the capping layer and is formed between the first dielectric layer and the first gate electrode, wherein the barrier layer has a U-shaped cross section defining two upper ends in direct contact with a bottom surface of the second gate electrode;
wherein the low-k layer is formed between the second dielectric layer and the capping layer.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the low-k layer comprises an air gap formed between the second dielectric layer and the capping layer, wherein the air gap has an opening formed between the upper surface of the second dielectric layer and the upper surface of the capping layer, such that the third dielectric layer is disposed on the low-k layer, wherein the opening of the air gap is directly sealed by the third dielectric layer.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the third dielectric layer is disposed over and in direct contact with the low-k layer and the second dielectric layer and entirely covers the upper surface of the second dielectric layer, the upper surface of the capping layer, and the upper surface of the low-k layer.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the upper surface of the capping layer is coplanar with the upper surface of the second dielectric layer.

### Claim 5 (depends on 1)

The memory device of claim 1, further comprising a fourth dielectric layer between the capping layer and the low-k layer, wherein the fourth dielectric layer has a dielectric constant less than that of the first dielectric layer or the second dielectric layer, wherein the low-k layer is formed between the second dielectric layer and the fourth dielectric layer, wherein an upper surface of the fourth dielectric layer is entirely covered by the third dielectric layer, wherein the fourth dielectric layer is in direct contact between the capping layer and the low-k layer.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the second dielectric layer and the fourth dielectric layer are formed of a same dielectric material.

### Claim 7 (depends on 3)

The memory device of claim 3, wherein the third dielectric layer extends over and in direct contact with the upper surfaces of the low-k layer and the second dielectric layer.

### Claim 8 (depends on 3)

The memory device of claim 3, wherein the third dielectric layer has a first thickness directly over the low-k layer and a second thickness directly over the second dielectric layer, wherein the first thickness is greater than the second thickness.

### Claim 9

A memory device, comprising:
a substrate;
a first gate electrode arranged within the substrate;
a capping layer arranged within the substrate and over the first gate electrode;
a first dielectric layer laterally surrounding the capping layer;
a second dielectric layer laterally surrounding the capping layer and laterally surrounded by the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are spaced apart from each other;
an air gap formed between the first dielectric layer and the second dielectric layer, wherein the air gap has an opening formed between an upper surface of the first dielectric layer and an upper surface of the second dielectric layer, wherein the opening of the air gap is positioned at a same horizontal level of an upper surface of the capping layer;
a fourth dielectric layer disposed on and in direct contact with the upper surface of the first dielectric layer, the upper surface of the second dielectric layer, and the upper surface of the capping layer to seal the opening of the air gap; and
a second gate electrode arranged between and in direct contact with the first gate electrode and the capping layer, wherein the second gate electrode is in fluid communication with the air gap below the second dielectric layer, wherein the first dielectric layer is in direct contact with a sidewall of the second gate electrode, wherein a bottom surface of the second dielectric layer is positioned below a top surface of the second gate electrode.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the first dielectric layer has a dielectric constant greater than that of the second dielectric layer.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the second dielectric layer comprises silicon-carbon oxide.

### Claim 12 (depends on 9)

The memory device of claim 9, wherein the air gap extends below the second dielectric layer and separates the first dielectric layer from the second dielectric layer, wherein a bottom surface of the first dielectric layer is positioned below a bottom surface of the second dielectric layer, such that the air gap is formed not only between the first dielectric layer and the second dielectric layer but also below the bottom surface of the second dielectric layer.

### Claim 13 (depends on 9)

The memory device of claim 9, wherein a lower surface of the second gate electrode is coplanar with a bottom surface of the first dielectric layer, wherein the upper surface of the capping layer, the upper surface of the first dielectric layer, and the upper surface of the second dielectric layer are coplanar with each other.

### Claim 14 (depends on 9)

The memory device of claim 9, further comprising a third dielectric layer below the first dielectric layer, the second dielectric layer and the second gate electrode, and laterally surrounding the first gate electrode, wherein the first dielectric layer has an L-shaped cross section defining an upper vertical portion parallel to the second dielectric layer and a lower horizontal portion in direct contact with the third dielectric layer, wherein the second dielectric layer and the third dielectric layer are separated by the air gap.

### Claim 15 (depends on 14)

The memory device of claim 14, further comprising a barrier layer between the third dielectric layer and the first gate electrode, wherein an upper surface of the third dielectric layer is coplanar with an upper surface of the barrier layer.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein the barrier layer is arranged below the first dielectric layer and is covered by the first dielectric layer.

### Claim 17 (depends on 9)

The memory device of claim 9, further comprising a source/drain region disposed in the substrate on one side of the first dielectric layer, wherein the source/drain region has a bottom lower than a lower surface of the first dielectric layer.