# US 12,764,928 B2 · Hybrid gate dielectric access device for vertical three-dimensional memory

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- Number: US 12,764,928 B2
- Document ID: US12764928B2
- Status: Granted
- Kind: B2
- Application number: 18/542,299
- Filed: 2023-12-15
- Published: 2024-06-20
- Granted: 2026-10-13
- Earliest claimed: 2022-12-16
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kamal M. Karda; Haitao Liu; Scott E. Sills; Si-Woo Lee
- Web page: https://patentgrep.com/patent/US12764928B2

## CPC

- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/05: {Making the transistor}
- H10B 12/482: {Bit lines}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Systems, methods and apparatus are provided for a hybrid gate dielectric access device for vertical three-dimensional (3D) memory. The memory cell has a first horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. The first access device is operatively controlled by a first gate. A hybrid gate dielectric separates the gate from the channel region and a horizontally oriented storage node coupled to the second source/drain region of the access device.

## Claims

### Claim 1

A memory device, comprising:
a horizontally oriented access device having a first source/drain region and a second source/drain region separated by a channel region, the access device being operatively controlled by a gate;
a hybrid gate dielectric separating the gate from the channel region, wherein:
the hybrid gate dielectric comprises:
a first layer having a surface formed in contact with the channel region;
a second layer having a surface formed in contact with a surface of the first layer opposite the first layer surface formed in contact with the channel region; and
a third layer having a surface formed in contact with a surface of the second layer opposite the second layer surface formed in contact with the surface of the first layer;
the gate is formed in contact with a surface of the third layer opposite the third layer surface formed in contact with the surface of the second layer; and
the second layer has a vertical thickness (t2) which is less than a vertical thickness (t1) of the first layer and is less than a vertical thickness (t3) of the third layer; and
a horizontally oriented storage node coupled to the second source/drain region of the access device.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the hybrid gate dielectric is a multi-layer dielectric having a first dielectric material and a second dielectric material.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the first layer is formed of a first dielectric material, the second layer is a second dielectric material, and the third layer is formed of the first dielectric material.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the first dielectric material is a silicon dioxide (SiO2) dielectric material, and the second dielectric material is an aluminum oxide (AlOx) dielectric material.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the second dielectric material is a dielectric material having an atomic composition with a fixed negative charge density of at least −1e12/cm2.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the vertical thickness (t1) of the first layer is less than forty (40) angstroms (Å), and the vertical thickness (t3) of the third layer is less than 40 Å.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the gate is a gate all around (GAA) structure opposing the channel region.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the gate is a horizontally oriented gate, and the first source/drain region is coupled to a vertically oriented digit line.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the access device is a thin film transistor (TFT) and the storage node is a horizontally oriented capacitor.

### Claim 10

A memory device, comprising:
a horizontally oriented access device having a first source/drain region and a second source/drain region separated by a channel region, the access device being operatively controlled by a gate opposing the channel region;
a multi-layer gate dielectric having a first dielectric material and a second dielectric material separating the gate from the channel region, the second dielectric material being different from the first dielectric material, wherein:
the multi-layer gate dielectric comprises:
a first layer having a surface formed in contact with the channel region;
a second layer having a surface formed in contact with a surface of the first layer opposite the first layer surface formed in contact with the channel region; and
a third layer having a surface formed in contact with a surface of the second layer opposite the second layer surface formed in contact with the surface of the first layer;
the gate is formed in contact with a surface of the third layer opposite the third layer surface formed in contact with the surface of the second layer; and
the second layer has a vertical thickness (t2) which is less than a vertical thickness (t1) of the first layer and is less than a vertical thickness (t3) of the third layer;
a horizontally oriented storage node coupled to the second source/drain region of the access device; and
a vertically oriented digit line coupled to the first source/drain region of the access device.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the gate is a gate all around (GAA) structure separated from the channel region by the multi-layer gate dielectric.

### Claim 12 (depends on 10)

The memory device of claim 10, wherein the storage node is located in a same plane horizontally with the horizontally oriented access device.

### Claim 13

A method of forming vertical three-dimensional (3D) memory, comprising:
forming a first horizontally oriented thin film transistor (TFT) in a first horizontal tier of a multi-tier 3D memory, the first TFT having a first source/drain region and a second source/drain region separated by a channel region;
forming a multi-layer gate dielectric, having a first dielectric material as a first layer and a second dielectric material as a second layer, separating a gate from the channel region to form an access device, the second dielectric material being different from the first dielectric material, wherein the first dielectric material is formed to have a first vertical thickness (t1), and wherein the second dielectric material is formed to have a second vertical thickness (t2) which is less than the first vertical thickness (t1);
forming a horizontally oriented storage node coupled to the second source/drain region of the access device; and
forming a vertically oriented digit line coupled to the first source/drain region of the access device.

### Claim 14 (depends on 13)

The method of claim 13, forming the multi-layer gate dielectric, comprising:
forming a first layer having a surface in contact with the channel region;
forming a second layer having a surface formed in contact with the first layer;
forming a third layer having a surface formed in contact with the second layer; and
forming the gate in contact with a surface of the third layer.

### Claim 15 (depends on 13)

The method of claim 13, comprising:
forming a silicon dioxide (SiO2) layer as the first dielectric material; and
forming an aluminum oxide (Al2O3) layer as the second dielectric material.

### Claim 16 (depends on 13)

The method of claim 13, comprising forming the second dielectric material of a dielectric material having an atomic composition with a fixed negative charge density of at least −1e12/cm2.

### Claim 17 (depends on 13)

The method of claim 13, comprising forming the gate as a gate all around (GAA) structure separated from the channel region by the multi-layer gate dielectric.