A method for forming a storage device, comprising:
- providing a semiconductor substrate, and forming a plurality of active areas in the semiconductor substrate, wherein the plurality of active areas are spaced apart from each other by a plurality of first trenches and a plurality of second trenches extending along a first direction and a plurality of third trenches extending along a second direction, the plurality of first trenches and the plurality of second trenches communicate with the plurality of third trenches, the plurality of first trenches and the plurality of second trenches are spaced apart from each other in the second direction, a depth of each of the plurality of second trenches is less than a depth of each of the plurality of first trenches, and a depth of a region of each of the plurality of third trenches other than a communication region of each of the plurality of third trenches with each of the plurality of second trenches is greater than the depth of each of the plurality of second trenches;
- forming a bit line doped area in the semiconductor substrate at a bottom portion of each of the plurality of second trenches and at a bottom portion of the communication region of each of the plurality of third trenches with each of the plurality of second trenches;
- forming a first isolation layer in each of the plurality of first trenches and each of the plurality of third trenches, wherein a surface of the first isolation layer is lower than a surface of each of the plurality of active areas;
- forming a gate dielectric layer surrounding the plurality of active areas on surfaces of the plurality of active areas;
- forming, on a surface of the gate dielectric layer arranged on side walls of the plurality of active areas, a plurality of metal gates surrounding the plurality of active areas, wherein a top surface of each of the plurality of metal gates is lower than a top surface of each of the plurality of active areas;
- and
- forming a source area on the top surface of each of the plurality of active areas;
- wherein forming the plurality of metal gates comprises:
- forming a metal layer filling the plurality of first trenches, the plurality of third trenches and the plurality of second trenches on the surface of the gate dielectric layer and on the surface of the first isolation layer;
- etching back the metal layer to allow a top surface of the metal layer to be lower than the top surface of each of the plurality of active areas;
- and after etching back the metal layer, cutting the metal layer filing the plurality of third trenches along the second direction to form the plurality of metal gates surrounding the plurality of active areas on the surface of the gate dielectric layer arranged on the side walls of the plurality of active areas.