Semiconductor structure and method for forming semiconductor structure

A semiconductor structure, comprising:

• a base;
• a plurality of separate ring-shaped external electrode layers located on the base;
• a dielectric layer located on an inner sidewall of each external electrode layer;
• an internal electrode layer located on an inner sidewall of the dielectric layer and a surface of the base in a ring of each external electrode layer;
• a first conductive layer filling a space outside the ring of each external electrode layer, wherein the first conductive layer is in contact with a respective one of the external electrode layers, and the first conductive layer and the internal electrode layer are formed synchronously;
• a second conductive layer filling a space inside the ring of the internal electrode layer, wherein the second conductive layer is in contact with the internal electrode layer;
• an isolation layer covering the second conductive layer, the dielectric layer, the external electrode layers, and the internal electrode layer, wherein an opening exposing the first conductive layer and the external electrode layers is formed in the isolation layer;
• and
• a connection structure that is located on a surface of the isolation layer and in the opening and is directly connected with the first conductive layer and each external electrode layer.

A method for forming a semiconductor structure, comprising:

• providing a base;
• forming a sacrifice layer and a support layer located on the sacrifice layer on the base;
• removing a part of the support layer and a part of the sacrifice layer, to form a plurality of capacitor vias in the support layer and the sacrifice layer;
• forming external electrode layers on sidewall surfaces of the capacitor vias;
• forming a dielectric material layer sidewall surfaces of the external electrode layers, bottom surfaces of the capacitor vias, and a surface of the support layer;
• removing the dielectric material layer on the bottom surfaces of the capacitor vias and the surface of the support layer by a maskless etching process, wherein a remaining part of the dielectric material layer on the sidewall surfaces of the external electrode layers forms a dielectric layer;
• removing remaining sacrifice layer between the external electrode layers to form a cavity at a position where the remaining sacrifice layer has been removed;
• forming an internal electrode layer on a surface of the dielectric layer and a bottom surface of each capacitor via;
• forming a first conductive layer completely filling the cavity, wherein the first conductive layer is in contact with a respective one of the external electrode layers;
• forming a second conductive layer completely filling a remaining part of each capacitor via on the internal electrode layer;
• forming an isolation layer covering the second conductive layer, the dielectric layer, the external electrode layers, the internal electrode layer, and the support layer;
• forming a plurality of openings exposing the first conductive layer and the external electrode layers in the isolation layer;
• and
• forming a connection structure electrically connected with the first conductive layer and the external electrode layers on a surface of the isolation layer and in the openings.