# US 12,764,922 B2 · Semiconductor structure

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- Number: US 12,764,922 B2
- Document ID: US12764922B2
- Status: Granted
- Kind: B2
- Application number: 18/664,305
- Filed: 2024-05-15
- Published: 2025-10-23
- Granted: 2026-10-13
- Earliest claimed: 2024-04-18
- Assignees: Powerchip Semiconductor Manufacturing Corporation
- Applicants: Powerchip Semiconductor Manufacturing Corporation
- Inventors: Jih-Chao Chiu; Yu-Shan Wu; Yuan-Ming Liu; Chee-Wee Liu
- Web page: https://patentgrep.com/patent/US12764922B2

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor structure including a substrate, gate layers, channel layers, and gate dielectric layers is provided. The gate layers and the channel layers are stacked on the substrate. The gate layers are separated from each other. Each of the gate layers surrounds the corresponding channel layer. Two adjacent gate layers are located between two adjacent channel layers. The gate dielectric layers are located between the gate layers and the channel layers.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
gate layers and channel layers stacked on the substrate, wherein the gate layers are separated from each other, each of the gate layers surrounds the corresponding channel layer, and two adjacent gate layers are located between two adjacent channel layers;
gate dielectric layers located between the gate layers and the channel layers; and
transistor devices, wherein the transistor devices comprise the gate layers, the channel layers, and the gate dielectrics layer, wherein
a portion of the lowermost gate layer is located between the substrate and the lowermost channel layer,
a portion of the lowermost gate dielectric layer is located between the substrate and the lowermost channel layer, and
at least two of the transistor devices are connected in parallel.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein the substrate comprises a silicon substrate or a glass substrate.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein materials of the gate layers comprise TiN, Al, Ti, Pd, Cr, Cu, Mo, or combinations thereof.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein materials of the channel layers comprise oxide semiconductor materials or semiconductor materials.

### Claim 5 (depends on 4)

The semiconductor structure according to claim 4, wherein the oxide semiconductor materials comprise InGaZnO, InSnO, In2O3, InZnO, ZnO, GaO, ZnInSnO, or ZnSnO.

### Claim 6 (depends on 4)

The semiconductor structure according to claim 4, wherein the semiconductor materials comprise Si, Ge, SiGe, GeSn, GaAs, GaSe, SiC, GaN, InP, AlGaAs, InGaP, or ZnSe.

### Claim 7 (depends on 1)

The semiconductor structure according to claim 1, wherein materials of the gate dielectric layers comprise high dielectric constant dielectric materials.

### Claim 8 (depends on 7)

The semiconductor structure according to claim 7, wherein the high dielectric constant dielectric materials comprise Al2O3, HfO2, TiO2, ZrO2, La2O3, Y2O3, Ta2O5, or HfSiO4.

### Claim 9 (depends on 1)

The semiconductor structure according to claim 1, further comprising:
first doped regions and second doped regions located in the channel layers, wherein the first doped regions and the second doped regions are located on opposite sides of the gate layers.

### Claim 10 (depends on 9)

The semiconductor structure according to claim 9, wherein the transistor devices further comprise the first doped regions and the second doped regions.

### Claim 11 (depends on 10)

The semiconductor structure according to claim 10, wherein the transistor devices comprise a write transistor device and a read transistor device.

### Claim 12 (depends on 11)

The semiconductor structure according to claim 11, wherein the write transistor comprises at least two of the transistor devices connected in parallel.

### Claim 13 (depends on 11)

The semiconductor structure according to claim 11, wherein the first doped region of the write transistor is electrically connected to the gate layer of the read transistor.

### Claim 14 (depends on 13)

The semiconductor structure according to claim 13, wherein a portion of the lowermost dielectric layer is located in a portion of the lowermost gate layer.

### Claim 15 (depends on 1)

The semiconductor structure according to claim 1, further comprising:
sacrificial layers located aside the gate layers and located between the channel layers.

### Claim 16 (depends on 1)

The semiconductor structure according to claim 1, further comprising:
dielectric layers located on the gate layers.