# US 12,764,921 B2 · Memory device, method of manufacturing memory device, and electronic apparatus including memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,764,921 B2 - Document ID: US12764921B2 - Status: Granted - Kind: B2 - Application number: 18/318,794 - Filed: 2023-05-17 - Published: 2023-11-23 - Granted: 2026-10-13 - Earliest claimed: 2022-05-19 - Assignees: Institute of Microelectronics, Chinese Academy of Sciences - Applicants: Institute of Microelectronics, Chinese Academy of Sciences - Inventors: Huilong Zhu - Web page: https://patentgrep.com/patent/US12764921B2 ## CPC - H10B 12/00: Dynamic random access memory [DRAM] devices - H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells} - H10W 29/00: Generic parts of integrated devices, not otherwise provided for - H10W 29/01: {Manufacture or treatment} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction relative to a substrate. The first connection line layer includes a plurality of first conductive lines extending parallel in a first direction. One of the second and third connection line layers includes a plurality of conductive lines extending parallel in a second direction intersecting the first direction. The fourth connection line layer includes a plurality of fourth conductive lines extending parallel in a third direction. A memory cell is provided at an intersection of conductive lines. Each memory cell includes first to third transistors stacked in the vertical direction. A fifth connection line layer is provided above the memory cell, and includes a plurality of fifth conductive lines extending in a fourth direction intersecting the third direction. ## Claims ### Claim 1 A memory device, comprising: a first connection line layer, a second connection line layer, a third connection line layer, and a fourth connection line layer that are sequentially disposed in a vertical direction with respect to a substrate, wherein the first connection line layer comprises a plurality of first conductive lines extending parallel to each other in a first direction, one of the second connection line layer and the third connection line layer comprises a plurality of conductive lines extending parallel to each other in a second direction intersecting the first direction, and the fourth connection line layer comprises a plurality of fourth conductive lines extending parallel to each other in a third direction; a plurality of memory cells, wherein each memory cell extends vertically from a corresponding first conductive line in the first connection line layer and respectively forms electrical connections with the second connection line layer or a corresponding conductive line in the second connection line layer, the third connection line layer or a corresponding conductive line in the third connection line layer, and a corresponding fourth conductive line in the fourth connection line layer, and each memory cell comprises a first transistor, a second transistor, and a third transistor that are stacked on each other in the vertical direction, wherein the first transistor comprises: a first active layer, comprising a first source/drain region electrically connected with the second connection line layer or the corresponding conductive line in the second connection line layer, a second source/drain region, and a channel region between the first source/drain region of the first transistor and the second source/drain region of the first transistor in the vertical direction; a first gate dielectric layer on the first active layer; and a first gate conductor layer on the first gate dielectric layer, wherein the first gate conductor layer extends towards the corresponding first conductive line in the first connection line layer to be electrically connected to the corresponding first conductive line in the first connection line layer, wherein the second transistor comprises: a second active layer, comprising a first source/drain region, a second source/drain region electrically connected with the third connection line layer or the corresponding conductive line in the third connection line layer, and a channel region between the first source/drain region of the second transistor and the second source/drain region of the second transistor in the vertical direction, wherein the second source/drain region of the first transistor and the first source/drain region of the second transistor are close to each other and electrically connected with each other; a second gate dielectric layer on the second active layer; and a second gate conductor layer on the second gate dielectric layer, wherein the second gate conductor layer and the first gate conductor layer are electrically isolated from each other, and wherein the third transistor comprises: a third active layer, comprising a first source/drain region electrically connected with the second gate conductor layer, a second source/drain region electrically connected with the corresponding fourth conductive line in the fourth connection line layer, and a channel region between the first source/drain region of the third transistor and the second source/drain region of the third transistor in the vertical direction; a third gate dielectric layer on the third active layer; and a third gate conductor layer on the third gate dielectric layer, and a fifth connection line layer above the memory cell, wherein the fifth connection line layer comprises a plurality of fifth conductive lines extending in a fourth direction intersecting the third direction, and the third gate conductor layer of each memory cell is electrically connected to a corresponding fifth conductive line in the fifth connection line layer, wherein the first active layer, the second active layer, and the third active layer are self-aligned in the vertical direction. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein portions where the first active layer, the second active layer and the third active layer are adjacent to each other are substantially aligned in the vertical direction. ### Claim 3 (depends on 2) The memory device according to claim 2, wherein portions where an outer sidewall of the first active layer, an outer sidewall of the second active layer and an outer sidewall of the third active layer are adjacent to each other are substantially coplanar in the vertical direction. ### Claim 4 (depends on 1) The memory device according to claim 1, wherein each memory cell is surrounded by at least one of the second connection line layer or the corresponding conductive line in the second connection line layer, the third connection line layer or the corresponding conductive line in the third connection line layer, and the corresponding fourth conductive line in the fourth connection line layer. ### Claim 5 (depends on 1) The memory device according to claim 1, wherein the other of the second connection line layer and the third connection line layer is an integrated conductive plate. ### Claim 6 (depends on 1) The memory device according to claim 1, wherein the first active layer and the second active layer are provided by a same semiconductor layer. ### Claim 7 (depends on 6) The memory device according to claim 6, wherein the second source/drain region of the first transistor and the first source/drain region of the second transistor are regions in the semiconductor layer, which are located between a top surface of the first gate conductor layer and a bottom surface of the second gate conductor layer in the vertical direction. ### Claim 8 (depends on 6) The memory device according to claim 6, wherein the semiconductor layer is in a shape of a vertically extending ring, and an outer sidewall of the ring-shaped semiconductor layer is in physical contact with the second connection line layer or the corresponding conductive line in the second connection line layer at a lower portion and in physical contact with the third connection line layer or the corresponding conductive line in the third connection line layer at an upper portion. ### Claim 9 (depends on 8) The memory device according to claim 8, wherein the first gate dielectric layer extends along an inner sidewall of the ring-shaped semiconductor layer, an inner space of the first gate dielectric layer is filled with the first gate conductor layer, and the first gate conductor layer extends towards the corresponding first conductive line in the first connection line layer and is in physical contact with the corresponding first conductive line in the first connection line layer. ### Claim 10 (depends on 8) The memory device according to claim 8, wherein the second gate dielectric layer has a vertical extending portion extending along an inner sidewall of the ring-shaped semiconductor layer and a bottom portion, an inner space of the second gate dielectric layer is filled with the second gate conductor layer, and the first gate conductor layer and the second gate conductor layer are electrically isolated from each other through the bottom portion of the second gate dielectric layer. ### Claim 11 (depends on 8) The memory device according to claim 8, wherein the third active layer has a bottom portion and a vertical extending portion extending vertically upward from the bottom portion of the third active layer, wherein the bottom portion of the third active layer is electrically connected with the second gate conductor layer, and the vertical extending portion of the third active layer is in physical contact with the corresponding fourth conductive line in the fourth connection line layer. ### Claim 12 (depends on 11) The memory device according to claim 11, wherein the bottom portion of the third active layer is in physical contact with the second gate conductor layer. ### Claim 13 (depends on 11) The memory device according to claim 11, wherein the memory cell further comprises: a connection portion between the second transistor and the third transistor, wherein the bottom portion of the third active layer is electrically connected with the second gate conductor layer through the connection portion. ### Claim 14 (depends on 11) The memory device according to claim 11, wherein the third gate dielectric layer extends along an inner wall of the third active layer, and an inner space of the third gate dielectric layer is filled with the third gate conductor layer. ### Claim 15 (depends on 11) The memory device according to claim 11, wherein the ring-shaped semiconductor layer is substantially aligned with the vertical extending portion of the third active layer in the vertical direction. ### Claim 16 (depends on 11) The memory device according to claim 11, further comprising: a first gate length control layer between the second connection line layer and the third connection line layer, wherein the first gate length control layer comprises a first gate length control pad disposed around the memory cell, a highest part of a top surface of the first gate conductor layer is higher than a bottom surface of the first gate length control pad, and a lowest part of a bottom surface of the second gate conductor layer is lower than a top surface of the first gate length control pad; and/or a second gate length control layer between the third connection line layer and the fourth connection line layer, wherein the second gate length control layer comprises a second gate length control pad disposed around the memory cell, and a lowest part of a bottom surface of the third gate conductor layer is lower than a top surface of the second gate length control pad. ### Claim 17 (depends on 11) The memory device according to claim 11, wherein the memory cell further comprises: an isolation portion in a form of spacer between the semiconductor layer and the third active layer. ### Claim 18 (depends on 17) The memory device according to claim 17, wherein the ring-shaped semiconductor layer, the vertical extending portion of the third active layer and an outer sidewall of the isolation portion are substantially coplanar in the vertical direction. ### Claim 19 (depends on 1) The memory device according to claim 1, wherein at least one of the first active layer, the second active layer, and the third active layer comprises indium gallium zinc oxide. ### Claim 20 (depends on 1) The memory device according to claim 1, wherein the second active layer comprises a semiconductor material with a relatively high mobility, and the third active layer comprises a semiconductor material with a relatively low leakage or a relatively large bandgap width. ### Claim 21 (depends on 1) The memory device according to claim 1, wherein the memory cell further comprises: an isolation portion in a form of spacer between the second active layer and the third active layer, wherein the first active layer, the second active layer, the third active layer, and the isolation portion are self-aligned in the vertical direction. ### Claim 22 (depends on 1) The memory device according to claim 1, wherein the memory device is a dynamic random access memory, the first conductive line corresponds to a read word line, the corresponding conductive line of one of the second connection line layer and the third connection line layer corresponds to a read bit line, the corresponding conductive line of the other of the second connection line layer and the third connection line layer corresponds to a ground plane, the fourth conductive line corresponds to a write bit line, and the fifth conductive line corresponds to a write word line. ### Claim 23 (depends on 1) An electronic apparatus, comprising the memory device according to claim 1. ### Claim 24 (depends on 23) The electronic apparatus according to claim 23, wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.