Homogeneous/ heterogeneous integration system with high performance computing and high storage volume

An integration system, comprising:

• a first monolithic die with a processing unit circuit;
• and
• a second monolithic die with a plurality of SRAM arrays;
• wherein the first monolithic die is physically separate from the second monolithic die, and the first monolithic die is electrically connected to the second monolithic die;
• wherein the integration system includes no high bandwidth memory (HBM);
• wherein the plurality of SRAM arrays or the processing unit circuit comprises a PMOS transistor and an NMOS transistor within a semiconductor substrate;
• the PMOS transistor has a first source region, a first drain region and a first isolation structure used to isolate a bottom of the first source region or the first drain region from the semiconductor substrate;
• the NMOS transistor has a second source region, a second drain region and a second isolation structure used to isolate a bottom of the second source region or the second drain region from the semiconductor substrate;
• wherein the first source or the first drain region has a first lightly doped region laterally extending from a sidewall of the semiconductor substrate, a first heavily doped region laterally extending from a most lateral edge of the first lightly doped region, and a first metal region laterally connected to a most lateral edge of the first heavily doped region;
• or
• wherein the second source or the second drain region has a second lightly doped region laterally extending from a sidewall of the semiconductor substrate, a second heavily doped region laterally extending from a most lateral edge of the second lightly doped region, and a second metal region laterally connected to a most lateral edge of the first heavily doped region.

An integration system, comprising:

• a substrate with an original horizontal surface;
• a first monolithic circuit with a processing unit circuit;
• and
• a second monolithic circuit with a plurality of SRAM arrays, wherein the plurality of SRAM arrays are between 2-20G Bytes;
• wherein the first monolithic circuit is electrically connected to the second monolithic circuit, the first monolithic circuit is formed in a first monolithic die and the second monolithic circuit is formed in a second monolithic die;
• wherein the first monolithic die and the second monolithic die are enclosed in a single package, or the first monolithic die and the second monolithic die are enclosed in a first package and a second package respectively;
• wherein the plurality of SRAM arrays or the processing unit circuit comprises a transistor within the substrate;
• the transistor comprises a source region and a drain region, and a shallow trench isolation (STI) is within the substrate and adjacent to the transistor, the STI has a top surface higher than the original horizontal surface of the substrate and surrounds the source region or the drain region;
• wherein the source region or the drain region has a lightly doped region laterally extending from a sidewall of the substrate, a heavily doped region laterally extending from a most lateral edge of the lightly doped region, and a metal region laterally connected to a most lateral edge of the heavily doped region.