# US 12,764,437 B2 · Image sensor with shared low conversion gain capacitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,764,437 B2 - Document ID: US12764437B2 - Status: Granted - Kind: B2 - Application number: 18/955,563 - Filed: 2024-11-21 - Published: 2026-05-21 - Granted: 2026-10-13 - Earliest claimed: 2024-11-21 - Assignees: OmniVision Technologies, Inc. - Applicants: Omnivision Technologies, Inc. - Inventors: Takayuki Goto; Sang Joo Lee; Keiji Mabuchi - Web page: https://patentgrep.com/patent/US12764437B2 ## CPC - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract An image sensor comprising a pixel cell array is described. The pixel cell array includes a plurality of pixel cells arranged in rows and columns. Individual pixel cells included in the plurality of pixel cells each includes one or more photodiodes configured to photogenerate image charge in response to incident light, a first floating diffusion, a second floating diffusion, a third floating diffusion, a dual floating diffusion transistor coupled between the first floating diffusion and the second floating diffusion, a lateral overflow transistor coupled between the first floating diffusion and the third floating diffusion, and a shared low conversion gain capacitor. The dual floating diffusion transistor and the lateral overflow transistor are coupled in parallel to the first floating diffusion. The second floating diffusion is coupled between the shared low conversion gain capacitor and the first floating diffusion. ## Claims ### Claim 1 An image sensor, comprising: a pixel cell array including a plurality of pixel cells arranged in rows and columns, wherein individual pixel cells included in the plurality of pixel cells each includes: one or more photodiodes configured to photogenerate image charge in response to incident light; a first floating diffusion, a second floating diffusion, and a third floating diffusion, wherein the first floating diffusion is coupled to receive the image charge from the one or more photodiodes; a dual floating diffusion transistor coupled between the first floating diffusion and the second floating diffusion; a lateral overflow transistor coupled between the first floating diffusion and the third floating diffusion, wherein the dual floating diffusion transistor and the lateral overflow transistor are coupled in parallel to the first floating diffusion; and a shared low conversion gain capacitor coupled to the dual floating diffusion transistor, wherein the second floating diffusion is coupled between the shared low conversion gain capacitor and the first floating diffusion. ### Claim 2 (depends on 1) The image sensor of claim 1, wherein the plurality of pixel cells includes a first pixel cell and a second pixel cell adjacent to the first pixel cell, and wherein the shared low conversion gain capacitor of the first pixel cell is coupled to the shared low conversion gain capacitor of the second pixel cell. ### Claim 3 (depends on 2) The image sensor of claim 2, wherein the shared low conversion gain capacitor included in each of the plurality of pixel cells corresponds to a metal-oxide-metal capacitor, wherein the plurality of pixel cells each further include a lateral overflow integration capacitor, and wherein the third floating diffusion is coupled between the lateral overflow integration capacitor and the first floating diffusion for each of the plurality of pixel cells to receive overflow image charges from the one or more photodiodes, wherein a capacitance of the lateral overflow integration capacitor is greater than the shared low conversion gain capacitor. ### Claim 4 (depends on 2) The image sensor of claim 2, wherein the shared low conversion gain capacitor includes a metal strip formed in a metallization region of the image sensor for each of the plurality of pixel cells, and wherein the metal strip of the shared low conversion gain capacitor included in the first pixel cell is coupled to the metal strip of the shared low conversion gain capacitor included in the second pixel cell. ### Claim 5 (depends on 4) The image sensor of claim 4, further comprising a ground line formed in the metallization region and arranged parallel to both the metal strip of the shared low conversion gain capacitor included in the first pixel cell and the metal strip of the shared low conversion gain capacitor included in the second pixel cell, wherein the image sensor further includes a plurality of bitlines coupled to the pixel cell array, and wherein the ground line, the metal strip included in the first pixel cell, and the metal strip included in the second pixel cell are parallel to a bitline included in the plurality of bitlines. ### Claim 6 (depends on 2) The image sensor of claim 2, wherein the plurality of pixel cells further include a third pixel cell and a fourth pixel cell, wherein the first, second, third, and fourth pixel cells are positioned in a same column included in the columns of the pixel cell array, wherein the second pixel cell is row-adjacent to the first pixel cell and the third pixel cell, wherein the fourth pixel cell is row-adjacent to the third pixel cell, and wherein the shared low conversion gain capacitor of the first pixel cell and the shared low conversion gain capacitor the second pixel cell are further coupled to: (i) the shared low conversion gain capacitor of the third pixel cell but not the shared low conversion gain capacitor of the fourth pixel cell; or (ii) the shared low conversion gain capacitor of the third pixel cell and the shared low conversion gain capacitor of the fourth pixel cell. ### Claim 7 (depends on 2) The image sensor of claim 2, further comprising a binning transistor coupled between the shared low conversion gain capacitor of the first pixel cell and the shared low conversion gain capacitor of the second pixel cell such that the shared low conversion gain capacitor of the first pixel cell is selectively coupled to the shared low conversion gain capacitor of the second pixel cell. ### Claim 8 (depends on 2) The image sensor of claim 2, wherein the first pixel cell and the second pixel cell are positioned in a same column included in the columns of the pixel cell array, and wherein the dual floating diffusion transistor of the second pixel cell is configured to be off during a readout period for the first pixel cell, wherein the readout period for the first pixel cell includes at least a high conversion gain mode and a low conversion gain mode, wherein conversion gain associated with the low conversion gain mode is less than conversion gain associated with the high conversion gain mode. ### Claim 9 (depends on 8) The image sensor of claim 8, wherein an off voltage for the dual floating diffusion transistor of the second pixel cell is lower than an off voltage for the dual floating diffusion transistor of the first pixel cell during an integration period for the first pixel cell, and wherein the dual floating diffusion transistor of the second pixel cell is configured to be off throughout the readout period of the first pixel cell. ### Claim 10 (depends on 1) The image sensor of claim 1, further comprising control circuitry configured to apply a first voltage to a dual floating diffusion gate electrode included in the dual floating diffusion transistor of the first pixel cell and a second voltage to a lateral overflow gate electrode included in the lateral overflow transistor of the first pixel cell during a high conversion gain mode included in a readout period for the first pixel cell, wherein the first voltage is greater than the second voltage. ### Claim 11 (depends on 1) The image sensor of claim 1, wherein the individual pixel cells included in the plurality of pixel cells each further includes: a first source-follower transistor and a second source-follower transistor, wherein a first source-follower gate electrode included in the first source-follower transistor is coupled to a second source-follower gate electrode included in second source-follower transistor; and a first row select transistor and a second row select transistor, and wherein the first source-follower gate electrode and the second source-follower gate electrode are both disposed between a first row select gate electrode included in the first row select transistor and a second row select gate electrode included in the second row select transistor. ### Claim 12 (depends on 1) The image sensor of claim 1, wherein the individual pixel cells included in the plurality of pixel cells each further includes: a first source-follower transistor and a second source-follower transistor, wherein a first source-follower gate electrode included in the first source-follower transistor is coupled to a second source-follower gate electrode included in second source-follower transistor; and a source/drain region coupled between a dual floating diffusion gate electrode included in the dual floating diffusion transistor and a lateral overflow gate electrode included in the lateral overflow transistor, and wherein the first source-follower gate electrode and the second source-follower gate electrode are coupled to the first floating diffusion and the source/drain region. ### Claim 13 (depends on 1) The image sensor of claim 1, wherein gate electrodes associated with pixel transistor circuitry included in the plurality of pixel cells are arranged symmetrically to have at least two axes of symmetry extending over the first floating diffusion included in a first pixel cell included in the plurality of pixel cells. ### Claim 14 (depends on 13) The image sensor of claim 13, wherein the gate electrodes included in the pixel transistor circuitry for the individual pixel cells included in the plurality of pixel cells each further includes a plurality of source-follower gate electrodes, a plurality of row select gate electrodes, a plurality of reset gate electrodes, a dual floating diffusion gate electrode, and a lateral overflow gate electrode. ### Claim 15 (depends on 1) The image sensor of claim 1, further comprising control circuitry configured to apply an off voltage to a dual floating diffusion gate electrode associated with the dual floating diffusion transistor of a first pixel cell included in the plurality of pixel cells during an integration period for the first pixel cell, an intermediate voltage to the dual floating diffusion gate electrode during a high conversion gain mode of a readout period for the first pixel cell, and an on voltage to the dual floating diffusion gate electrode during a low conversion gain mode of the readout period for the first pixel cell, wherein the intermediate voltage and the on voltage are each positive voltage levels, and wherein the on voltage is greater than the intermediate voltage. ### Claim 16 An imaging system, comprising: a pixel cell array, including a plurality of pixel cells arranged in rows and columns, wherein individual pixel cells included in the plurality of pixel cells each includes: one or more photodiodes configured to photogenerate image charge in response to incident light; a first floating diffusion and a second floating diffusion, wherein the first floating diffusion is coupled to receive the image charge from the one or more photodiodes; a dual floating diffusion transistor coupled between the first floating diffusion and the second floating diffusion; and a shared low conversion gain capacitor coupled to the dual floating diffusion transistor and selectively coupled to the first floating diffusion; a plurality of bitlines coupled to the pixel cell array; control circuitry coupled to the pixel cell array to control operation of the pixel cell array; and readout circuitry coupled to the pixel cell array through the plurality of bitlines to readout image data representative of the image charge from the pixel cell array, wherein the plurality of pixel cells includes a first pixel cell and a second pixel cell adjacent to the first pixel cell, and wherein the shared low conversion gain capacitor of the first pixel cell is coupled to the shared low conversion gain capacitor of the second pixel cell. ### Claim 17 (depends on 16) The imaging system of claim 16, wherein the first pixel cell is row-adjacent to the second pixel cell, wherein a metal electrode of the shared low conversion gain electrode included in the first pixel cell is coupled to a metal electrode of the shared low conversion gain electrode included in the second pixel cell, and wherein the first metal electrode and the second metal electrode are parallel to a bitline included in the plurality of bitlines. ### Claim 18 (depends on 16) The imaging system of claim 16, wherein the dual floating diffusion transistor of the second pixel cell is configured to be off by the control circuitry during an integration period and a readout period for the first pixel cell, wherein the readout period for the first pixel cell includes a high conversion gain mode and a low conversion gain mode. ### Claim 19 (depends on 18) The imaging system of claim 18, wherein during the integration period for the first pixel cell, the control circuitry is configured to apply a first off voltage to a dual floating diffusion gate electrode included in the dual floating diffusion transistor of the first pixel cell and a second off voltage to a dual floating diffusion gate electrode included in the dual floating diffusion transistor of the second pixel cell, and wherein the second off voltage is lower than the first off voltage. ### Claim 20 (depends on 16) The imaging system of claim 16, wherein the control circuitry is configured to apply an off voltage to a dual floating diffusion gate electrode associated with the dual floating diffusion transistor of the first pixel cell during an integration period for the first pixel cell, an intermediate voltage to the dual floating diffusion gate electrode during a high conversion gain mode of a readout period for the first pixel cell, and an on voltage to the dual floating diffusion gate electrode during a low conversion gain mode of the readout period for the first pixel cell, wherein the intermediate voltage and the on voltage are each positive voltage levels, and wherein the on voltage is greater than the intermediate voltage.