Decoder for decoding data in a PAM-10 format because of 1+0.5D pulse shaping, decoder device using the decoder, and receiver using the decoder device

A decoder device comprising:

• a number (N) of decoders, each of which includes a first demultiplexer, a signal amplifier and a number (P) of decoder units, where N≥2 and P≥2;
• said first demultiplexers of said decoders cooperating with each other to receive a feed-in data signal that originated from an input data signal in a pulse amplitude modulation (PAM)-4 format, and to demultiplex the feed-in data signal into a number (N) of to-be-amplified data signals that are respectively outputted by said first demultiplexers and that are in a PAM-10 format because of 1+0.5 D pulse shaping;
• for each of said decoders,
• said signal amplifier being connected to said first demultiplexer to receive the to-be-amplified data signal outputted by said first demultiplexer, and performing amplification and level shifting on the to-be-amplified data signal so as to generate a to-be-decoded data signal,
• each of said decoder units including a second demultiplexer, a three-bit analog to digital converter (ADC) and a comparator, and
• said second demultiplexers of said decoder units being connected to said signal amplifier, and cooperating with each other to receive the to-be-decoded data signal from said signal amplifier, and to demultiplex the to-be-decoded data signal into a number (P) of demultiplexed data signals that are respectively outputted by said second demultiplexers;
• and
• for each of said decoder units of said decoders,
• each of said three-bit ADC and said comparator being connected to said second demultiplexer to receive the demultiplexed data signal outputted by said second demultiplexer, and
• said three-bit ADC and said comparator cooperating with each other to decode the demultiplexed data signal into a decoded signal that is four-bits wide, where said three-bit ADC performs analog to digital conversion on the demultiplexed data signal so as to generate a portion of the decoded signal that is three-bits wide, and said comparator compares the demultiplexed data signal with a reference voltage so as to generate another portion of the decoded signal that is one-bit wide.

A receiver comprising:

• a phase interpolator receiving a clock input, and performing phase interpolation on the clock input to generate a number (N) of interpolated clock signals, where N≥2 and a phase shift of each of the interpolated clock signals with respect to the clock input is adjustable;
• a decoder device including a number (N) of decoders, each of which includes a deskewer, a first demultiplexer, a signal amplifier and a number (P) of decoder units, where P≥2;
• for each of said decoders,
• said deskewer being connected to said phase interpolator to receive a respective one of the interpolated clock signals, and delaying the respective one of the interpolated clock signals so as to generate a deskewed clock signal, and
• said first demultiplexer being connected to said deskewer to receive the deskewed clock signal;
• said first demultiplexers of said decoders cooperating with each other to receive a feed-in data signal that originated from an input data signal in a pulse amplitude modulation (PAM)-4 format, and to demultiplex, based on the deskewed clock signals generated by said deskewers of said decoders, the feed-in data signal into a number (N) of to-be-amplified data signals that are respectively outputted by said first demultiplexers and that are in a PAM-10 format because of 1+0.5 D pulse shaping;
• for each of said decoders,
• said signal amplifier being connected to said first demultiplexer to receive the to-be-amplified data signal outputted by said first demultiplexer, and performing amplification and level shifting on the to-be-amplified data signal so as to generate a to-be-decoded data signal,
• each of said decoder units including a second demultiplexer, a three-bit analog to digital converter (ADC) and a comparator, and
• said second demultiplexers of said decoder units being connected to said signal amplifier, and cooperating with each other to receive the to-be-decoded data signal from said signal amplifier, and to demultiplex the to-be-decoded data signal into a number (P) of demultiplexed data signals that are respectively outputted by said second demultiplexers;
• for each of said decoder units of said decoders,
• each of said three-bit ADC and said comparator being connected to said second demultiplexer to receive the demultiplexed data signal outputted by said second demultiplexer, and
• said three-bit ADC and said comparator cooperating with each other to decode the demultiplexed data signal into a decoded signal that is four-bits wide, where said three-bit ADC performs analog to digital conversion on the demultiplexed data signal so as to generate a portion of the decoded signal that is three-bits wide, and said comparator compares the demultiplexed data signal with a reference voltage so as to generate another portion of the decoded signal that is one-bit wide;
• and
• a processor connected to said decoder device to receive a decoded output that originated from the decoded signals generated by said three-bit ADCs and said comparators of said decoder units of said decoders, and further connected to said phase interpolator;
• based on the decoded output, said processor generating an output data signal, and performing adaptive calibration on said phase interpolator to adjust the phase shifts of the interpolated clock signals.