# US 12,763,998 B2 · High-gain, low-sensitivity, current-integrating decision-feedback equalizer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,998 B2 - Document ID: US12763998B2 - Status: Granted - Kind: B2 - Application number: 18/979,958 - Filed: 2024-12-13 - Published: 2026-06-18 - Granted: 2026-10-13 - Earliest claimed: 2024-12-13 - Assignees: QUALCOMM Incorproated - Applicants: QUALCOMM Incorporated - Inventors: Lejie Lu; Younwoong Chung; Yu Song; Dong Ren - Web page: https://patentgrep.com/patent/US12763998B2 ## CPC - H04L 25/03878: {Line equalisers; line build-out devices} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An equalizing circuit has a first current summer and a first sampler. The first current summer may be configured to sum currents representative of a data signal and a first plurality of feedback signals when enabled by a first control signal. The first current summer may be enabled when the first control signal is in a first signaling state and disabled when the control signal is in a first signaling state. The first sampler may be configured to sample an output of the first current summer in accordance with timing provided by a first sampling clock signal. The first control signal may be in the first signaling state for a duration that is longer than a unit interval that defines the interval in which a bit of data is encoded in the data signal. ## Claims ### Claim 1 An equalizing circuit comprising: a first current summer configured to sum currents representative of a data signal and a first plurality of feedback signals when enabled by a first control signal, wherein the first current summer is enabled when the first control signal is in a first signaling state and disabled when the first control signal is in a second signaling state; and a first sampler configured to sample an output of the first current summer in accordance with timing provided by a first sampling clock signal, wherein the first control signal is in the first signaling state for a duration that is longer than a unit interval that defines an interval in which a bit of data is encoded in the data signal. ### Claim 2 (depends on 1) The equalizing circuit of claim 1, wherein the first control signal has a period that is twice the duration of one unit interval. ### Claim 3 (depends on 1) The equalizing circuit of claim 1, further comprising: a first duty cycle control circuit adapted to configure a duty cycle greater than 50% for the first control signal. ### Claim 4 (depends on 1) The equalizing circuit of claim 1, wherein the first sampler is configured to sample signaling state at the output of the first current summer at an edge in the first sampling clock signal and while the first control signal is in the first signaling state. ### Claim 5 (depends on 1) The equalizing circuit of claim 1, further comprising: a second current summer configured to sum currents representative of the data signal and a second plurality of feedback signals when enabled by a second control signal, wherein the second current summer is enabled when the second control signal is in the first signaling state and disabled when the control signal is in the second signaling state; and a second sampler configured to sample an output of the second current summer in accordance with timing provided by a second sampling clock signal, wherein the second control signal is in the first signaling state for a duration that is longer than one unit interval. ### Claim 6 (depends on 5) The equalizing circuit of claim 5, wherein the second control signal has a period that is twice the duration of a unit interval. ### Claim 7 (depends on 5) The equalizing circuit of claim 5, further comprising: a second duty cycle control circuit adapted to configure a duty cycle greater than 50% for the second control signal. ### Claim 8 (depends on 5) The equalizing circuit of claim 5, wherein the second sampler is configured to sample signaling state at the output of the second current summer at an edge in the second sampling clock signal and while the second control signal is in the first signaling state. ### Claim 9 (depends on 5) The equalizing circuit of claim 5, wherein the second control signal is a phase shifted version of the first control signal and wherein the second sampling clock signal is an inverted version of the first sampling clock signal. ### Claim 10 (depends on 5) The equalizing circuit of claim 5, wherein the first plurality of feedback signals includes delayed versions of the output of the first sampler and delayed versions of the output of the second sampler, and wherein the second plurality of feedback signals includes delayed versions of the output of the second sampler and delayed versions of the output of the first sampler. ### Claim 11 An apparatus, comprising: means for summing currents representative of a data signal and a first plurality of feedback signals and configured to provide a first summed output signal, wherein the currents representative of the data signal and the first plurality of feedback signals are summed when a first control signal is in a first signaling state; and means for sampling the first summed output signal in accordance with timing provided by a first sampling clock signal, wherein the first control signal is in the first signaling state for a duration that is longer than a unit interval that defines an interval in which a bit of data is encoded in the data signal. ### Claim 12 (depends on 11) The apparatus of claim 11, further comprising: means for summing currents representative of the data signal and a second plurality of feedback signals and configured to provide a second summed output signal, wherein the currents representative of the data signal and the second plurality of feedback signals are summed when a second control signal is in the first signaling state; and means for sampling the second summed output signal in accordance with timing provided by a second sampling clock signal, wherein the second control signal is in the first signaling state for a duration that is longer than one unit interval. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein each of the first control signal and the second control signal has a period that is twice the duration of a unit interval and a duty cycle greater than 50%. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the second control signal is a phase shifted version of the first control signal and wherein the second sampling clock signal is an inverted version of the first sampling clock signal. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the first plurality of feedback signals includes delayed versions of the output of the means for sampling the first summed output signal and delayed versions of the output of the means for sampling the second summed output signal, and wherein the second plurality of feedback signals includes delayed versions of the output of the means for sampling the second summed output signal and delayed versions of the output of the means for sampling the first summed output signal. ### Claim 16 A method for equalizing a data signal received over a serial data link, comprising: summing currents representative of a data signal and a first plurality of feedback signals to provide a first summed output signal, wherein the currents representative of the data signal and the first plurality of feedback signals are summed when a first control signal is in a first signaling state; and sampling the first summed output signal in accordance with timing provided by a first sampling clock signal, wherein the first control signal is in the first signaling state for a duration that is longer than a unit interval that defines the interval an interval in which a bit of data is encoded in the data signal. ### Claim 17 (depends on 16) The method of claim 16, further comprising: summing currents representative of the data signal and a second plurality of feedback signals to provide a second summed output signal, wherein the currents representative of the data signal and the second plurality of feedback signals are summed when a second control signal is in the first signaling state; and sampling the second summed output signal in accordance with timing provided by a second sampling clock signal, wherein the second control signal is in the first signaling state for a duration that is longer than one unit interval. ### Claim 18 (depends on 17) The method of claim 17, wherein each of the first control signal and the second control signal has a period that is twice the duration of a unit interval and a duty cycle greater than 50%. ### Claim 19 (depends on 17) The method of claim 17, wherein the second control signal is a phase shifted version of the first control signal and wherein the second sampling clock signal is an inverted version of the first sampling clock signal. ### Claim 20 (depends on 17) The method of claim 17, wherein the first plurality of feedback signals includes delayed versions of the first summed output signal and delayed versions of the second summed output signal, and wherein the second plurality of feedback signals includes delayed versions of the second summed output signal and delayed versions of the first summed output signal.