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US 12,763,996 B1Granted
Decision feedback equalization circuit
AssigneeCadence Design Systems, Inc.
InventorsRiju Biswas, Swarajit Manna
Life of this patent
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Abstract
The present disclosure relates to circuits and methods for decision feedback equalization. Embodiments may include a sum amplifier and a tap network in electrical communication with the sum amplifier. Embodiments may further include a single slicer in electrical communication with the tap network. The single slicer may include at least one capacitive digital-to-analog converter configured to provide capacitive feedback to a source of the single slicer.
Claims16
A decision feedback equalization circuit, comprising:
- a sum amplifier;
- a tap network in electrical communication with the sum amplifier;
- and
- a single slicer in electrical communication with the tap network, the single slicer including at least one capacitive digital-to-analog converter configured to provide capacitive feedback to a source of the single slicer, wherein the at least one capacitive digital-to-analog converter includes a P-side capacitive digital-to-analog converter and an N-side capacitive digital-to-analog converter, wherein capacitive feedback is provided to the source of the single slicer without providing feedback to the sum amplifier.
1 more element
A decision feedback equalization method, comprising:
- electrically connecting a sum amplifier, a tap network and a single slicer;
- and
- providing capacitive feedback to a source of the single slicer using at least one capacitive digital-to-analog converter associated with the single slicer;
- and
- providing capacitive feedback to the source of the single slicer without providing feedback to the sum amplifier, wherein the at least one capacitive digital-to-analog converter includes a P-side capacitive digital-to-analog converter and an N-side capacitive digital-to-analog converter.
2 more elements
Dependencies are inferred from the claim text.