# US 12,763,792 B2 · Methods of constructing and using low-power QDE-zipper codes, and systems, apparatuses, methods, and non-transitory computer-readable storage devices employing same

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- Number: US 12,763,792 B2
- Document ID: US12763792B2
- Status: Granted
- Kind: B2
- Application number: 18/671,663
- Filed: 2024-05-22
- Published: 2025-11-27
- Granted: 2026-10-13
- Earliest claimed: 2024-05-22
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Bashirreza Karimi; Yoones Hashemi Toroghi; Hamid Ebrahimzad
- Web page: https://patentgrep.com/patent/US12763792B2

## CPC

- H03M 7/3066: {by means of a mask or a bit-map}
- H03M 7/6005: {Decoder aspects}
- H03M 7/6011: {Encoder aspects}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A method for encoding information bits using a zipper code. The zipper is associated with a real buffer for receiving the information bits, a first virtual buffer, a second virtual buffer, and two mapping functions φ1 and φ2. Each row of the real buffer, a corresponding row of the first virtual buffer, and a corresponding row of the second virtual buffer form a codeword of a component code. The two mapping functions φ1 and φ2 are for mapping each group of c bits in each row of the real buffer to c bits in one or more subsequent rows of the first virtual buffer and to c bits in one or more subsequent row of the second virtual buffer, respectively. The c bits in the first virtual buffer are in different rows thereof, and/or the c bits in the second virtual buffer are in different rows thereof.

## Claims

### Claim 1

A method for encoding a plurality of information bits into a plurality of coded bits, the method comprising:
encoding the plurality of information bits into the plurality of coded bits using a zipper code associated with a first mapping function φ1 and a second mapping function φ2;
wherein the zipper code is associated with a real buffer, a first virtual buffer, and a second virtual buffer, each comprising a plurality of sections;
wherein each section of the real buffer, a corresponding section of the first virtual buffer, and a corresponding section of the second virtual buffer form a codeword of a component code;
wherein the real buffer is for receiving the plurality of information bits into the plurality of sections thereof;
wherein the first mapping function φ1 and the second mapping function φ2 are for mapping each group of c bits, where c>1 is an integer, in each section of the real buffer to c mapped bits in one or more first subsequent sections of the first virtual buffer and to c mapped bits in one or more second subsequent sections of the second virtual buffer, respectively;
wherein the c mapped bits in the first virtual buffer are in different sections thereof, and/or the c mapped bits in the second virtual buffer are in different sections thereof; and
wherein, when bit positions of the sections of the real buffer, bit positions of the sections of the first virtual buffer, and bit positions of the sections of the second virtual buffer are separately and correspondingly numbered,
for each section of the real buffer,
the bit positions of the bits in the section of the real buffer, the bit positions of the corresponding mapped buts in any one of the one or more first subsequent sections of the first virtual buffer, and the bit positions of the corresponding mapped bits in any one of the one or more second subsequent sections of the second virtual buffer only have one bit position in common.

### Claim 2 (depends on 1)

The method of claim 1, wherein, when the bits of each section of the first virtual buffer are indexed from 1 to m (m>1 is an integer), the bits of each section of the second virtual buffer are indexed from m+1 to 2m, and the bits of each section of the real buffer are indexed from 2m+1 to 3m,
the first mapping function φ1 maps j-th bit (j=2m+1, . . . , 3m) of i-th row of the real buffer to j1-th bit of i1-th row of the first virtual buffer, and
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where [x] is a function returning a smallest integer that is greater than or equal to x, [y] is a function returning a greatest integer that is smaller than y, and α % b represents a modulo function returning a remainder of α divided by b, and
the second mapping function φ2 maps the j-th bit of the i-th row of the real buffer to j2-th bit of i2-th row of the second virtual buffer, and
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### Claim 3 (depends on 1)

The method of claim 1, wherein c=3.

### Claim 4

One or more processors functionally coupled to one or more non-transitory computer-readable storage devices, the one or more non-transitory computer-readable storage devices comprising computer-executable instructions, wherein the instructions, when executed, cause the one or more processors to perform a method comprising:
encoding a plurality of information bits into a plurality of coded bits using a zipper code associated with a first mapping function φ1 and a second mapping function φ2;
wherein the zipper code is associated with a real buffer, a first virtual buffer, and a second virtual buffer, each comprising a plurality of sections;
wherein each section of the real buffer, a corresponding section of the first virtual buffer, and a corresponding section of the second virtual buffer form a codeword of a component code;
wherein the real buffer is for receiving the plurality of information bits into the plurality of sections thereof;
wherein the first mapping function φ1 and the second mapping function φ2 are for mapping each group of c bits, where c>1 is an integer, in each section of the real buffer to c mapped bits in one or more first subsequent sections of the first virtual buffer and to c mapped bits in one or more second subsequent sections of the second virtual buffer, respectively;
wherein the c mapped bits in the first virtual buffer are in different sections thereof, and/or the c mapped bits in the second virtual buffer are in different sections thereof; and
wherein, when bit positions of the sections of the real buffer, bit positions of the sections of the first virtual buffer, and bit positions of the sections of the second virtual buffer are separately and corresondingly numbered,
for each section of the real buffer,
the bit positions of the bits in the section of the real buffer, the bit positions of the corresponding mapped bits in any one of the one or more first subsequent sections of the first virtual buffer, and the bit positions of the corresponding mapped bits in any one of the one or more second subsequent sections of the second virtual buffer only have one bit position in common.

### Claim 5 (depends on 4)

The one or more processors of claim 4, wherein, when the bits of each section of the first virtual buffer are indexed from 1 to m (m>1 is an integer), the bits of each section of the second virtual buffer are indexed from m+1 to 2m, and the bits of each section of the real buffer are indexed from 2m+1 to 3m,
the first mapping function φ1 maps j-th bit (j=2m+1, . . . , 3m) of i-th row of the real buffer to j1-th bit of i1-th row of the first virtual buffer, and
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where [x] is a function returning a smallest integer that is greater than or equal to x, [y] is a function returning a greatest integer that is smaller than y, and α % b represents a modulo function returning a remainder of α divided by b, and
the second mapping function φ2 maps the j-th bit of the i-th row of the real buffer to j2-th bit of i2-th row of the second virtual buffer, and
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.

### Claim 6 (depends on 4)

The one or more processors of claim 4, wherein c=3.

### Claim 7

One or more non-transitory computer-readable storage media comprising computer-executable instructions, wherein the instructions, when executed, cause one or more processors to perform a method comprising:
encoding a plurality of information bits into a plurality of coded bits using a zipper code associated with a first mapping function φ1 and a second mapping function φ2;
wherein the zipper code is associated with a real buffer, a first virtual buffer, and a second virtual buffer, each comprising a plurality of sections;
wherein each section of the real buffer, a corresponding section of the first virtual buffer, and a corresponding section of the second virtual buffer form a codeword of a component code;
wherein the real buffer is for receiving the plurality of information bits into the plurality of sections thereof;
wherein the first mapping function φ1 and the second mapping function φ2 are for mapping each group of c bits, where c>1 is an integer, in each section of the real buffer to c mapped bits in one or more first subsequent sections of the first virtual buffer and to c mapped bits in one or more second subsequent sections of the second virtual buffer, respectively;
wherein the c mapped bits in the first virtual buffer are in different sections thereof, and/or the c mapped bits in the second virtual buffer are in different sections thereof; and
wherein, when bit positions of thee sections of the real buffer, bit positions of the sections of the first virtual buffer, and bit positions of the sections of the second virtual buffer are separately and corresponding numbered,
for each section of the real buffer,
the bit positions of the bits in the section of the real buffer, the bit positions of the corresponding mapped bits in any one of the one or more first subsequent sections of the first virtual buffer, and the bit positions of the corresponding mapped bits in any one of the one or more second subsequent sections of the second virtual buffer only have one bit position in common.

### Claim 8 (depends on 7)

The one or more non-transitory computer-readable storage media of claim 7, wherein, when the bits of each section of the first virtual buffer are indexed from 1 to m (m>1 is an integer), the bits of each section of the second virtual buffer are indexed from m+1 to 2m, and the bits of each section of the real buffer are indexed from 2m+1 to 3m,
the first mapping function φ1 maps j-th bit (j=2m+1, . . . , 3m) of i-th row of the real buffer to j1-th bit of i1-th row of the first virtual buffer, and
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otherwise
,
where [x] is a function returning a smallest integer that is greater than or equal to x, [y] is a function returning a greatest integer that is smaller than y, and α % b represents a modulo function returning α remainder of a divided by b, and
the second mapping function φ2 maps the j-th bit of the i-th row of the real buffer to j2-th bit of i2-th row of the second virtual buffer, and
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.

### Claim 9 (depends on 7)

The one or more non-transitory computer-readable storage media of claim 7, wherein c=3.

### Claim 10

A method comprising:
decoding a plurality of coded bits into a plurality of information bits using a zipper code associated with a first mapping function φ1 and a second mapping function φ2;
wherein the zipper code is associated with a real buffer, a first virtual buffer, and a second virtual buffer, each comprising a plurality of sections;
wherein each section of the real buffer, a corresponding section of the first virtual buffer, and a corresponding section of the second virtual buffer form a codeword of a component code;
wherein the real buffer is for receiving the plurality of coded bits into the plurality of sections thereof;
wherein the first mapping function φ1 and the second mapping function φ2 are for mapping bits in each section of the real buffer to a plurality of first subsequent sections of the first virtual buffer and to bits in one or more second subsequent sections of the second virtual buffer, respectively; and
wherein said decoding the plurality of coded bits comprises:
determining that a syndrome of a first codeword is nonzero, the first codeword comprising a first one of the plurality of sections of the real buffer, and corresponding to plurality of second codewords comprising bits mapped from the bits of the first one of the plurality of sections of the real buffer,
calculating syndromes of the plurality of second codewords,
determining values of a plurality of variables, each of the plurality of variables corresponding to one of the plurality of second codewords, and having a value of binary zero if the syndrome of the corresponding second codeword is zero or a value of binary one if the syndrome of the corresponding second codeword is nonzero, and
correcting a plurality of bits of the first one of the plurality of sections of the real buffer by determining values thereof based on the values of the plurality of variables.

### Claim 11 (depends on 10)

The method of claim 10, wherein said correcting the plurality of bits of the first one of the plurality of sections of the real buffer comprises:
for each bit of the first one of the plurality of sections of the real buffer, combining a subset of the plurality of variables to obtain an indication, the subset of the plurality of variables corresponding to a subset of the plurality of second codewords that comprise the mapped bits mapped from the bit of the first one of the plurality of sections of the real buffer, and the indication indicating whether or not the corresponding bit of the first one of the plurality of sections of the real buffer is corrupted; and
for P indications that indicate the corresponding bit is corrupted, selecting a possible value combination of the P corresponding bits that causes the first codeword to have a zero-value syndrome as the values thereof.

### Claim 12 (depends on 11)

The method of claim 11, wherein the selected possible value combination of the P corresponding bits is a possible value combination that has a smallest Hamming weight and causes the first codeword to have the zero-value syndrome.

### Claim 13

One or more processors functionally coupled to one or more non-transitory computer-readable storage devices, the one or more non-transitory computer-readable storage devices comprising computer-executable instructions, wherein the instructions, when executed, cause the one or more processors to perform a method comprising:
decoding a plurality of coded bits into a plurality of information bits using a zipper code associated with a first mapping function φ1 and a second mapping function φ2;
wherein the zipper code is associated with a real buffer, a first virtual buffer, and a second virtual buffer, each comprising a plurality of sections;
wherein each section of the real buffer, a corresponding section of the first virtual buffer, and a corresponding section of the second virtual buffer form a codeword of a component code;
wherein the real buffer is for receiving the plurality of coded bits into the plurality of sections thereof;
wherein the first mapping function φ1 and the second mapping function φ2 are for mapping bits in each section of the real buffer to a plurality of first subsequent sections of the first virtual buffer and to bits in one or more second subsequent sections of the second virtual buffer, respectively; and
wherein said decoding the plurality of coded bits comprises:
determining that a syndrome of a first codeword is nonzero, the first codeword comprising a first one of the plurality of sections of the real buffer, and corresponding to plurality of second codewords comprising bits mapped from the bits of the first one of the plurality of sections of the real buffer,
calculating syndromes of the plurality of second codewords,
determining values of a plurality of variables, each of the plurality of variables corresponding to one of the plurality of second codewords, and having a value of binary zero if the syndrome of the corresponding second codeword is zero or a value of binary one if the syndrome of the corresponding second codeword is nonzero, and
correcting a plurality of bits of the first one of the plurality of sections of the real buffer by determining values thereof based on the values of the plurality of variables.

### Claim 14 (depends on 13)

The one or more processors of claim 13, wherein said correcting the plurality of bits of the first one of the plurality of sections of the real buffer comprises:
for each bit of the first one of the plurality of sections of the real buffer, combining a subset of the plurality of variables to obtain an indication, the subset of the plurality of variables corresponding to a subset of the plurality of second codewords that comprise the mapped bits mapped from the bit of the first one of the plurality of sections of the real buffer, and the indication indicating whether or not the corresponding bit of the first one of the plurality of sections of the real buffer is corrupted; and
for P indications that indicate the corresponding bit is corrupted, selecting a possible value combination of the P corresponding bits that causes the first codeword to have a zero-value syndrome as the values thereof.

### Claim 15 (depends on 14)

The one or more processors of claim 14, wherein the selected possible value combination of the P corresponding bits is a possible value combination that has a smallest Hamming weight and causes the first codeword to have the zero-value syndrome.

### Claim 16

One or more non-transitory computer-readable storage media comprising computer-executable instructions, wherein the instructions, when executed, cause one or more processors to perform a method comprising:
decoding a plurality of coded bits into a plurality of information bits using a zipper code associated with a first mapping function φ1 and a second mapping function φ2;
wherein the zipper code is associated with a real buffer, a first virtual buffer, and a second virtual buffer, each comprising a plurality of sections;
wherein each section of the real buffer, a corresponding section of the first virtual buffer, and a corresponding section of the second virtual buffer form a codeword of a component code;
wherein the real buffer is for receiving the plurality of coded bits into the plurality of sections thereof;
wherein the first mapping function φ1 and the second mapping function φ2 are for mapping bits in each section of the real buffer to a plurality of first subsequent sections of the first virtual buffer and to bits in one or more second subsequent sections of the second virtual buffer, respectively; and
wherein said decoding the plurality of coded bits comprises:
determining that a syndrome of a first codeword is nonzero, the first codeword comprising a first one of the plurality of sections of the real buffer, and corresponding to plurality of second codewords comprising bits mapped from the bits of the first one of the plurality of sections of the real buffer,
calculating syndromes of the plurality of second codewords,
determining values of a plurality of variables, each of the plurality of variables corresponding to one of the plurality of second codewords, and having a value of binary zero if the syndrome of the corresponding second codeword is zero or a value of binary one if the syndrome of the corresponding second codeword is nonzero, and
correcting a plurality of bits of the first one of the plurality of sections of the real buffer by determining values thereof based on the values of the plurality of variables.

### Claim 17 (depends on 16)

The one or more non-transitory computer-readable storage media of claim 16, wherein said correcting the plurality of bits of the first one of the plurality of sections of the real buffer comprises:
for each bit of the first one of the plurality of sections of the real buffer, combining a subset of the plurality of variables to obtain an indication, the subset of the plurality of variables corresponding to a subset of the plurality of second codewords that comprise the mapped bits mapped from the bit of the first one of the plurality of sections of the real buffer, and the indication indicating whether or not the corresponding bit of the first one of the plurality of sections of the real buffer is corrupted; and
for P indications that indicate the corresponding bit is corrupted, selecting a possible value combination of the P corresponding bits that causes the first codeword to have a zero-value syndrome as the values thereof.

### Claim 18 (depends on 17)

The one or more non-transitory computer-readable storage media of claim 17, wherein the selected possible value combination of the P corresponding bits is a possible value combination that has a smallest Hamming weight and causes the first codeword to have the zero-value syndrome.