# US 12,763,791 B2 · Analog-to-digital converter circuit, digital filter circuit, and control method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,791 B2 - Document ID: US12763791B2 - Status: Granted - Kind: B2 - Application number: 18/760,894 - Filed: 2024-07-01 - Published: 2025-01-30 - Granted: 2026-10-13 - Earliest claimed: 2023-07-24 - Assignees: Nuvoton Technology Corporation - Applicants: Nuvoton Technology Corporation - Inventors: Cheng-Chih Wang - Web page: https://patentgrep.com/patent/US12763791B2 ## CPC - H03M 3/496: {Details of sampling arrangements or methods} - H03M 3/436: {characterised by the order of the loop filter, e.g. error feedback type} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An analog-to-digital converter (ADC) circuit including a receiving circuit and a delta-sigma ADC is provided. The receiving circuit receives a first analog input and a second analog input, and uses the first or second analog input as an output signal according to a control signal. The delta-sigma ADC converts the output signal to input data. The delta-sigma ADC over-samples the input data to generate a plurality of sampling results and stores the sampling results. The delta-sigma ADC generates output data according to the sampling results. ## Claims ### Claim 1 An analog-to-digital converter (ADC) circuit, comprising: a receiver circuit receiving a first analog input and a second analog input and using the first analog input or the second analog input as an output signal according to a control signal; and a delta-sigma ADC converting the output signal to generate output data and comprising: a differential amplifier amplifying a difference between the output signal and a reference signal to generate an amplified signal; an integrator accumulating the amplified signal to generate an integrated signal; a quantizer quantizing the integrated signal to generate input data; a digital-to-analog converter (DAC) circuit converting the input data to generate the reference signal; and a digital filter circuit over-sampling the input data according to the control signal to generate the output data, wherein: in response to the control signal matching a predetermined state: the receiver circuit uses the first analog input as the output signal; the digital filter circuit over-samples the input data to generate a plurality of first sampled results and stores the first sampled results in a first register circuit; and the digital filter circuit generates the output data according to the first sampled results, in response to the control signal not matching the predetermined state: the receiver circuit uses the second analog input as the output signal; the digital filter circuit over-samples the input data to generate a plurality of second sampled results and stores the second sampled results in a second register circuit; and the digital filter circuit generates the output data according to the second sampled results, the digital filter circuit comprises: an integrator circuit comprising a plurality of integrators which are connected in series and store both the first sampled results and the second sampled results; a comb filter circuit comprising a plurality of comb filters which are connected in series and store both the first sampled results and the second sampled results; and a frequency reduction circuit coupled between the integrator circuit and the comb filter circuit. ### Claim 2 (depends on 1) The ADC circuit as claimed in claim 1, wherein the second sampled results are stored in the second register circuit while the digital filter circuit generates the output data according to the first sampled results. ### Claim 3 An analog-to-digital converter (ADC) circuit, comprising: a receiver circuit receiving a first analog input and a second analog input and using the first analog input or the second analog input as an output signal according to a control signal; and a delta-sigma ADC converting the output signal to generate output data and comprising: a differential amplifier amplifying a difference between the output signal and a reference signal to generate an amplified signal; an integrator accumulating the amplified signal to generate an integrated signal; a quantizer quantizing the integrated signal to generate input data; a digital-to-analog converter (DAC) circuit converting the input data to generate the reference signal; and a digital filter circuit over-sampling the input data according to the control signal to generate the output data, wherein: in response to the control signal matching a predetermined state: the receiver circuit uses the first analog input as the output signal; the digital filter circuit over-samples the input data to generate a plurality of first sampled results and stores the first sampled results in a first register circuit; and the digital filter circuit generates the output data according to the first sampled results, in response to the control signal not matching the predetermined state: the receiver circuit uses the second analog input as the output signal; the digital filter circuit over-samples the input data to generate a plurality of second sampled results and stores the second sampled results in a second register circuit; and the digital filter circuit generates the output data according to the second sampled results, the digital filter circuit comprises: an integrator circuit comprising: a first integrator comprising: a first adder adding the input data and a first register value to generate a first calculation value; a first selector circuit selecting the first calculation value as a first output value or a second output value according to the control signal; a first register storing the first output value; a second register storing the second output value; a second selector circuit selecting the first output value stored in the first register or the second output value stored in the second register as the first register value according to the control signal; a second integrator connected to the first integrator in series and comprising: a second adder adding the first calculation value and a second register value to generate a second calculation value; a third selector circuit selecting the second calculation value as a third output value or a fourth output value according to the control signal; a third register storing the third output value; a fourth register storing the fourth output value; a fourth selector circuit selecting the third output value stored in the third register or the fourth output value stored in the fourth register as the second register value according to the control signal; a frequency reduction circuit down-sampling the second calculation value to generate a processed value; a comb filter circuit comprising: a first comb filter comprising: a first subtractor subtracting a third register value from the processed value to generate a third calculation value; a fifth selector circuit selecting the processed value as a fifth output value or a sixth output value according to the control signal; a fifth register storing the fifth output value; a sixth register storing the sixth output value; a sixth selector circuit selecting the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third register value according to the control signal; a second comb filter comprising: a second subtractor subtracting a fourth register value from the third calculation value to generate a fourth calculation value; a seventh selector circuit selecting the third calculation value as a seventh output value or an eighth output value according to the control signal; a seventh register storing the seventh output value; an eighth register storing the eighth output value; an eighth selector circuit selecting the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth register value according to the control signal. ### Claim 4 (depends on 3) The ADC circuit as claimed in claim 3, wherein the first register circuit comprises the first register, the third register, the fifth register, and the seventh register, and the second register circuit comprises the second register, the fourth register, the sixth register, and the eighth register. ### Claim 5 (depends on 1) The ADC circuit as claimed in claim 1, further comprising: a first channel receiving the first analog input generated by a first sensing circuit and providing the first analog input to the receiver circuit; a second channel receiving the second analog input generated by a second sensing circuit and providing the second analog input to the receiver circuit. ### Claim 6 (depends on 5) The ADC circuit as claimed in claim 5, wherein: in response to the receiver circuit using the first analog input as the output signal, the digital filter circuit over-samples the input data to generate a plurality of first sampled results and stores the first sampled results in a first register circuit, in response to the receiver circuit using the second analog input as the output signal, the digital filter circuit over-samples the input data to generate a plurality of second sampled results and stores the second sampled results in a second register circuit, and the first register circuit is independent of the second register circuit. ### Claim 7 (depends on 1) The ADC circuit as claimed in claim 1, further comprising: a programmable gain amplifier coupled between the receiver circuit and the differential amplifier to amplify the output signal. ### Claim 8 (depends on 1) The ADC circuit as claimed in claim 1, further comprising: a control circuit directing the control signal to change between a first state and a second state. ### Claim 9 A digital filter circuit over-sampling input data to generate output data and comprising: an integrator circuit comprising: a first integrator comprising: a first adder adding the input data and a first register value to generate a first calculation value; a first selector circuit selecting the first calculation value as a first output value or a second output value according to a control signal; a first register storing the first output value; a second register storing the second output value; a second selector circuit selecting the first output value stored in the first register or the second output value stored in the second register as the first register value according to the control signal; a second integrator connected to the first integrator in series and comprising: a second adder adding the first calculation value and a second register value to generate a second calculation value; a third selector circuit selecting the second calculation value as a third output value or a fourth output value according to the control signal; a third register storing the third output value; a fourth register storing the fourth output value; a fourth selector circuit selecting the third output value stored in the third register or the fourth output value stored in the fourth register as the second register value according to the control signal; a frequency reduction circuit down-sampling the second calculation value to generate a processed value; a comb filter circuit comprising: a first comb filter comprising: a first subtractor subtracting a third register value from the processed value to generate a third calculation value; a fifth selector circuit selecting the processed value as a fifth output value or a sixth output value according to the control signal; a fifth register storing the fifth output value; a sixth register storing the sixth output value; a sixth selector circuit selecting the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third register value according to the control signal; a second comb filter comprising: a second subtractor subtracting a fourth register value from the third calculation value to generate a fourth calculation value; a seventh selector circuit selecting the third calculation value as a seventh output value or an eighth output value according to the control signal; a seventh register storing the seventh output value; an eighth register storing the eighth output value; an eighth selector circuit selecting the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth register value according to the control signal. ### Claim 10 (depends on 9) The digital filter circuit as claimed in claim 9, further comprising: a gain adjustment circuit shifting the fourth calculation value to generate the output data. ### Claim 11 (depends on 10) The digital filter circuit as claimed in claim 10, wherein a number of bits of output data is less than a number of bits of fourth calculation value. ### Claim 12 (depends on 9) The digital filter circuit as claimed in claim 9, wherein in response to the control signal matching a predetermined state: the first selector circuit selects the first calculation value as the first output value, the second selector circuit selects the first output value stored in the first register as the first register value, the third selector circuit selects the second calculation value as the third output value, the fourth selector circuit selects the third output value stored in the third register as the second register value, the fifth selector circuit selects the processed value as the fifth output value, the sixth selector circuit selects the fifth output value stored in the fifth register as the third register value, the seventh selector circuit selects the third calculation value as the seventh output value, and the eighth selector circuit selects the seventh output value stored in the seventh register as the fourth register value. ### Claim 13 (depends on 12) The digital filter circuit as claimed in claim 12, wherein in response to the control signal not matching the predetermined state: the first selector circuit selects the first calculation value as the second output value, the second selector circuit selects the second output value stored in the second register as the first register value, the third selector circuit selects the second calculation value as the fourth output value, the fourth selector circuit selects the fourth output value stored in the fourth register as the second register value, the fifth selector circuit selects the processed value as the sixth output value, the sixth selector circuit selects the sixth output value stored in the sixth register as the third register value, the seventh selector circuit selects the third calculation value as the eighth output value, and the eighth selector circuit selects the eighth output value stored in the eighth register as the fourth register value. ### Claim 14 (depends on 3) The ADC circuit as claimed in claim 3, wherein the second sampled results are stored in the second register circuit while the digital filter circuit generates the output data according to the first sampled results. ### Claim 15 (depends on 3) The ADC circuit as claimed in claim 3, further comprising: a first channel receiving the first analog input generated by a first sensing circuit and providing the first analog input to the receiver circuit; a second channel receiving the second analog input generated by a second sensing circuit and providing the second analog input to the receiver circuit. ### Claim 16 (depends on 15) The ADC circuit as claimed in claim 15, wherein: in response to the receiver circuit using the first analog input as the output signal, the digital filter circuit over-samples the input data to generate a plurality of first sampled results and stores the first sampled results in a first register circuit, in response to the receiver circuit using the second analog input as the output signal, the digital filter circuit over-samples the input data to generate a plurality of second sampled results and stores the second sampled results in a second register circuit, and the first register circuit is independent of the second register circuit. ### Claim 17 (depends on 3) The ADC circuit as claimed in claim 3, further comprising: a programmable gain amplifier coupled between the receiver circuit and the differential amplifier delta-sigma ADC to amplify the output signal. ### Claim 18 (depends on 3) The ADC circuit as claimed in claim 3, further comprising: a control circuit directing the control signal to change between a first state and a second state.