Successive approximation register A/D converter
AssigneeRohm Co., Ltd.
InventorHaruaki Nakamura
Life of this patent
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Abstract
A successive approximation register A/D converter (SARADC) has redundancy. An analog unit samples an analog input voltage and generates a comparison signal indicating a magnitude relationship between a threshold voltage corresponding to a control code and the analog input voltage. A logic unit generates, in an i-th (i≥1) cycle, a first value obtained by adding a weight of an (i+1)-th cycle to a control code of the i-th cycle and a second value obtained by subtracting the weight of the (i+1)-th cycle from the control code of the i-th cycle. When a comparison signal of the cycle is determined, the logic unit supplies one of the first value and the second value corresponding to the comparison signal to the analog unit 110 as a control code of the (i+1)-th cycle.
Claims7
A successive approximation register A/D converter having redundancy structured to convert an analog input voltage into a digital output, the successive approximation register A/D converter comprising:
- an analog unit structured to sample the analog input voltage and generate a comparison signal indicating a magnitude relationship between a threshold voltage corresponding to a control code and the analog input voltage;
- and
- a logic unit structured to generate the control code of a next cycle corresponding to the comparison signal for each cycle,
- wherein the logic unit is structured to generate, in an i-th (i≥1) cycle and before the determination of the comparison signal of the i-th cycle, both a first value obtained by adding a weight of an (i+1)-th cycle to the control code of the i-th cycle and a second value obtained by subtracting the weight of the (i+1)-th cycle from the control code of the i-th cycle, and
- wherein the logic unit is structured to, when the comparison signal of the i-th cycle is determined, supply one of the first value and the second value corresponding to the comparison signal to the analog unit as the control code of the (i+1)-th cycle.
Dependencies are inferred from the claim text.