Apparatus and method for wide input range successive approximation register (SAR) analog-to-digital converter (ADC) with integrated voltage attenuation
OwnerYuan-Ju Chaoinventor
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Abstract
The present invention relates to a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) capable of handling large input voltage ranges beyond the supply voltage (VDD) through integrated voltage attenuation. By introducing a series capacitor (Cx) between the input and the Digital-to-Analog Converter (DAC) capacitors, the SARADC achieves input voltage attenuation without the need for external resistor dividers. The proposed configuration supports both single-ended and differential modes, allowing the SARADC to process wide-ranging input voltages while minimizing power consumption, circuit complexity, and silicon area.
Claims19
A successive approximation register (SAR) Analog-to-Digital converter (ADC) comprising:
- (a) a series capacitor (Cx) and capacitive digital-to-analog converter (DAC) including a plurality of capacitors and switches connected to an input, a reference voltage or a ground,
- (b) a sampling circuit with switches configured to attenuate an input voltage that exceeds a supply voltage (VDD) by a predefined factor, allowing the ADC to process input signals exceeding the supply voltage,
- (c) a comparator and binary search logic, wherein the comparator output and binary search logic control the switches, and
- (d) multiple analog input channels, wherein one channel is configured to handle input voltages within the supply voltage and another channel is configured to handle input voltages exceeding the supply voltage.
A method of performing Successive approximation register (SAR) Analog-to-Digital (ADC) conversion, comprising:
- (a) providing a series capacitor (Cx) and capacitive digital-to-analog converter (DAC) comprising a plurality of capacitors and switches connected to input, a reference voltage or ground, and
- (b) providing a sampling circuit with switches configured to attenuate an input voltage that exceeds the supply voltage (VDD) by a predefined factor, allowing the ADC to process input signals exceeding the supply voltage, and
- (c) providing a comparator and binary search logic wherein the comparator output and binary search logic control the associated switches, and
- (d) sampling multiple analog input channels, wherein one channel is configured to handle input voltages within the supply voltage and another channel is configured to handle input voltages exceeding the supply voltage range.
Dependencies are inferred from the claim text.