# US 12,763,786 B2 · Direct current offset calibration for digital-to-analog conversion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,786 B2 - Document ID: US12763786B2 - Status: Granted - Kind: B2 - Application number: 18/746,894 - Filed: 2024-06-18 - Published: 2025-12-18 - Granted: 2026-10-13 - Earliest claimed: 2024-06-18 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Beomsoo Park; Ashok Swaminathan; Negar Rashidi - Web page: https://patentgrep.com/patent/US12763786B2 ## CPC - H03M 1/1014: {at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Certain aspects of the present disclosure provide techniques and apparatus for digital-to-analog conversion. An example apparatus generally includes a digital-to-analog converter (DAC), an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC, and a controller coupled to the DAC and the IADC. The controller is configured to determine a direct current (DC) offset associated with the DAC using the IADC and control a mission-mode digital input signal of the DAC based on the DC offset. ## Claims ### Claim 1 An apparatus for digital-to-analog conversion, comprising: a digital-to-analog converter (DAC); an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC; and a controller coupled to the DAC and the IADC, wherein the controller is configured to: determine a direct current (DC) offset associated with the DAC using the IADC; and control a digital input signal of the DAC based on the DC offset. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the IADC comprises a switch circuit coupled to the first output of the DAC. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the switch circuit is configured to: in a non-flip mode, couple the first output of the DAC to the first input of the IADC and a second output of the DAC to a second input of the IADC; and in a flip mode, couple the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein: the IADC is configured to: generate a non-flip-mode digital output signal based on a first output current of the DAC while the switch circuit is configured in the non-flip mode; and generate a flip-mode digital output signal based on a second output current of the DAC while the switch circuit is configured in the flip mode; and the controller is configured to determine the DC offset based on the non-flip-mode digital output signal and the flip-mode digital output signal. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the controller is configured to set a calibration-mode digital input signal of the DAC to a middle code, and wherein the IADC is configured to generate the non-flip-mode digital output signal and the flip-mode digital output signal while the calibration-mode digital input signal of the DAC is set to the middle code. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the IADC is configured to perform analog-to-digital conversion using delta-sigma modulation. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein: the IADC is configured to be coupled to another DAC after the DC offset associated with the DAC is determined; and the controller is configured to determine another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC. ### Claim 8 (depends on 1) The apparatus of claim 1, further comprising a current source circuit configured to: sink a first current from a first node coupled to the first input of the IADC; and sink a second current from a second node coupled to a second input of the IADC. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein an amount of the first current is the same as an amount of the second current. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein: the controller is configured to set a calibration-mode digital input signal of the DAC to a middle code; the IADC is configured to generate a first digital output signal based on a first output current of the DAC while the calibration-mode digital input signal is set to the middle code; the controller is configured to set the calibration-mode digital input signal of the DAC to the middle code minus one; the IADC is configured to generate a second digital output signal based on a second output current of the DAC while the calibration-mode digital input signal is set to the middle code minus one; and the controller is configured to determine the DC offset based on the first digital output signal and the second digital output signal. ### Claim 11 A method for digital-to-analog conversion, comprising: generating, via a digital-to-analog converter (DAC), a first output current based on a calibration-mode digital input signal; generating, via an incremental analog-to-digital converter (IADC), a first digital output signal based on the first output current; determining a direct current (DC) offset associated with the DAC based on the first digital output signal; and adjusting a digital input signal for the DAC based on the DC offset. ### Claim 12 (depends on 11) The method of claim 11, wherein the IADC comprises a switch circuit coupled to an output of the DAC. ### Claim 13 (depends on 12) The method of claim 12, further comprising: generating, via the IADC, a non-flip-mode digital output signal based on the first output current of the DAC while the switch circuit is configured in a non-flip mode; and generating, via the IADC, a flip-mode digital output signal based on a second output current of the DAC while the switch circuit is configured in a flip mode, wherein the DC offset is determined based on the non-flip-mode digital output signal and the flip-mode digital output signal. ### Claim 14 (depends on 13) The method of claim 13, further comprising: in the non-flip mode, coupling a first output of the DAC to a first input of the IADC and a second output of the DAC to a second input of the IADC using the switch circuit; and in the flip mode, coupling the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC using the switch circuit. ### Claim 15 (depends on 13) The method of claim 13, further comprising setting the calibration-mode digital input signal of the DAC to a middle code, wherein the non-flip-mode digital output signal and the flip-mode digital output signal are generated while the calibration-mode digital input signal of the DAC is set to the middle code. ### Claim 16 (depends on 11) The method of claim 11, further comprising: coupling the IADC to another DAC after the DC offset associated with the DAC is determined; and determining another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC. ### Claim 17 (depends on 11) The method of claim 11, further comprising: sinking a first current from a first node coupled to a first input of the IADC; and sinking a second current from a second node coupled to a second input of the IADC, wherein the first digital output signal is generated while the first current and the second current are being sunk from the first input and the second input of the IADC, respectively. ### Claim 18 (depends on 17) The method of claim 17, wherein an amount of the first current is the same as an amount of the second current. ### Claim 19 (depends on 11) The method of claim 11, further comprising: setting the calibration-mode digital input signal of the DAC to a middle code, wherein the first digital output signal is generated based on the first output current of the DAC while the calibration-mode digital input signal is set to the middle code; setting the calibration-mode digital input signal of the DAC to the middle code minus one; and generating a second digital output signal based on a second output current of the DAC while the calibration-mode digital input signal is set to the middle code minus one, wherein the DC offset is determined based on the first digital output signal and the second digital output signal. ### Claim 20 An apparatus for digital-to-analog conversion, comprising: a digital-to-analog converter (DAC) including a first output and a second output; and an incremental analog-to-digital converter (IADC) including a switch circuit, a first input selectively coupled to the first output of the DAC or the second output of the DAC via the switch circuit, and a second input selectively coupled to the first output of the DAC or the second output of the DAC via the switch circuit, wherein the switch circuit is configured to: in a non-flip mode, couple the first output of the DAC to the first input of the IADC and a second output of the DAC to a second input of the IADC; and in a flip mode, couple the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC.