# US 12,763,783 B2 · Closed loop DAC glitch mitigation

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- Number: US 12,763,783 B2
- Document ID: US12763783B2
- Status: Granted
- Kind: B2
- Application number: 18/227,027
- Filed: 2023-07-27
- Published: 2024-03-21
- Granted: 2026-10-13
- Earliest claimed: 2022-09-21
- Assignees: Analog Devices International Unlimited Company
- Applicants: Analog Devices International Unlimited Company
- Inventors: Murat Demirkan; Michael E. Harrell; Dennis A. Dempsey; Zahit Evren Kaya
- Web page: https://patentgrep.com/patent/US12763783B2

## CPC

- H03M 1/0604: {at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)}
- H03F 3/04: with semiconductor devices only
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS

## Abstract

A method of feedback control of an amplifier system includes driving multiple amplifier circuits using at least one digital-to-analog converter (DAC) circuit to set a system output of the amplifier system, operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady state target output, detecting a high glitch transition of the first set of DAC codes that is greater than a specified threshold transition, and changing to operating the at least one DAC circuit using a second set of DAC codes to set the system output to substantially the same steady state target output, wherein operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the at least one DAC circuit.

## Claims

### Claim 1

A method of feedback control of an amplifier system, the method comprising:
driving multiple amplifier circuits using at least one digital-to-analog converter (DAC) circuit to set a system output of the amplifier system;
sweeping a DAC code of the at least one DAC code over a specified range of DAC code values;
storing DAC glitch characteristic data for DAC code transitions in a system memory;
detecting a high-energy glitch transition using the stored DAC glitch magnitudes for the DAC code transitions;
operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady state target output;
detecting a high glitch condition at an output of the at least one DAC circuit when using the first set of DAC codes; and
changing to operating the at least one DAC circuit using a second set of DAC codes to set the system output to substantially the same steady state target output, wherein operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the least one DAC circuit.

### Claim 2 (depends on 1)

The method of claim 1, wherein detecting the high glitch condition includes detecting a high-energy glitch transition that is greater than a threshold glitch transition when operating the at least one DAC circuit using the first set of DAC codes.

### Claim 3 (depends on 1)

The method of claim 1, wherein detecting the high glitch condition includes identifying that the first set of DAC codes includes the a high-energy glitch transition associated with the high glitch condition when setting the system output to the steady state target output.

### Claim 4 (depends on 1)

The method of claim 1, including:
setting the system output to the steady state target output using a control loop that includes a feedback circuit path; and
wherein the changing to operating the at least one DAC circuit using a second set of DAC codes includes adding an offset to the control loop to operate the at least one DAC circuit using the second set of DAC codes.

### Claim 5 (depends on 4)

The method of claim 4, wherein the adding the offset to the control loop includes adding a programmable offset to the control loop using another DAC circuit.

### Claim 6 (depends on 1)

The method of claim 1, including:
applying an output of the at least one DAC circuit to an input of a first amplifier circuit and an input of a second amplifier circuit of the multiple amplifier circuits when operating the amplifier system in a first mode; and
applying the output of the at least one DAC circuit to the input of the first amplifier circuit and applying an output of another DAC circuit to the input of the second amplifier circuit in a second mode, wherein the second mode has a lower voltage output than the first mode.

### Claim 7 (depends on 1)

The method of claim 1, wherein the driving the multiple amplifier circuits includes:
driving multiple DAC channels, wherein each DAC channel includes a main DAC and an amplifier circuit, and the amplifier circuits of the DAC channels have different signal gain;
operating the main DAC circuits of the DAC channels using the first set of DAC codes and summing outputs of the DAC channels to set the system output; and
using a control loop to set the system output to the steady state target output and to change to operating the main DAC circuits using the second set of DAC codes to reduce ripple of the system output caused by the multiple DAC channels.

### Claim 8 (depends on 7)

The method of claim 7, including:
detecting a high-energy glitch transition that is greater than a threshold glitch transition when operating the at least one DAC circuit using the first set of DAC codes;
determining an offset using a magnitude of the high-energy glitch transition and current DAC code; and
selecting a set of DAC codes as the second set of DAC codes using the determined offset.

### Claim 9 (depends on 1)

The method of claim 1, including:
updating a DAC code of the at least one DAC circuit using DAC code values selected from the first set of DAC codes to set the system output to the steady state target output;
detecting when the DAC code of the at least one DAC circuit settles near a high-glitch DAC code transition when setting the system output to the steady state target output; and
updating the DAC code of the at least one DAC circuit using DAC code values selected from the second set of DAC codes in response to the detecting.

### Claim 10

An amplifier system including:
multiple digital to analog converter (DAC) circuits including a first DAC circuit and a second DAC circuit, wherein setting a DAC code in the DAC circuits sets an output of the at least one DAC circuit;
multiple amplifier circuits including a first amplifier circuit and a second amplifier circuit, wherein an output of the first DAC circuit is connected to an input of the first amplifier circuit;
a switch circuit configured to connect the output of the first DAC circuit to an input of the second amplifier circuit in a first mode, and connect the output of the second DAC circuit to the input of the second amplifier circuit in a second mode that has a lower voltage output range than the first mode;
a feedback circuit path connected to a system output of the amplifier system; and
a control circuit connected to at least one DAC circuit of the multiple DAC circuits and the feedback circuit path, wherein the control circuit is configured to:
operate the at least one DAC circuit using a first set of DAC codes to set the system output to a steady state output target; and
change to operating the at least one DAC circuit using a second set of DAC codes to maintain the same steady state output target and to reduce ripple at the system output caused by the at least one DAC circuit.

### Claim 11 (depends on 10)

The amplifier system of claim 10, including:
a control loop that includes the feedback circuit and the control circuit;
wherein the control circuit is configured to:
detect a high glitch transition of the first set of DAC codes that is greater than a threshold glitch transition; and
add an offset to the control loop to change to the selecting the DAC code from the second set of DAC codes.

### Claim 12 (depends on 11)

The amplifier system of claim 11, including:
another DAC circuit to add the offset to the control loop; and
wherein the control circuit is configured to set the offset according to a magnitude of the high glitch transition and one or more DAC codes values corresponding to the high glitch transition.

### Claim 13 (depends on 11)

The amplifier system of claim 11, including:
a summing node connected to outputs of the multiple amplifier circuits;
wherein the at least one DAC circuit includes multiple DAC circuits;
wherein the inputs of the multiple amplifier circuits are connected to the outputs of the multiple DAC circuits to form multiple DAC channels and the outputs of the multiple amplifier circuits are connected to the summing node; and
wherein the control circuit is configured to:
update DAC codes of the multiple DAC circuits to maintain the steady state output target; and
add the offset to the summing node to change to selecting the DAC codes from the second set of DAC codes.

### Claim 14 (depends on 11)

The amplifier system of claim 11,
wherein the multiple amplifier circuits include a first amplifier circuit and a second amplifier circuit, and the at least one DAC circuit includes a first DAC circuit connected to an input of the first amplifier circuit and a second DAC circuit connected to an input of the second amplifier circuit;
wherein the control circuit is configured to:
update the DAC codes of both the first DAC circuit and the second DAC circuit to apply an equal DAC output to the first amplifier circuit and the second amplifier circuit to set the system output to the steady state output target in a first mode; and
update the DAC code of only the first DAC circuit to set the system output to the steady state output target in a second mode, wherein the second mode has a lower output voltage range than the first mode.

### Claim 15 (depends on 10)

The amplifier system of claim 10, including:
a system memory; and
wherein the control circuit is configured to:
sweep a DAC code of the at least one DAC circuit over a specified range of DAC code values;
store DAC glitch characteristic data for DAC code transitions in the system memory; and
detect the high glitch transition using the stored DAC glitch magnitudes for the DAC code transitions.

### Claim 16 (depends on 10)

The amplifier system of claim 10,
wherein the feedback circuit path that includes an analog-to-digital converter (ADC) circuit operatively coupled to the system output; and
wherein the control circuit is configured to set the DAC code of the at least one DAC circuit to set a system output voltage to a steady state output target voltage.

### Claim 17 (depends on 10)

The amplifier system of claim 10, including:
a sense impedance at the system output;
wherein the feedback circuit path that includes an analog-to-digital converter (ADC) circuit operatively coupled to the sense impedance; and
wherein the control circuit is configured to set the DAC code of the at least one DAC circuit to set a system output current to a steady state target output current.

### Claim 18

A power supply system having closed loop control, the power supply system comprising:
multiple digital to analog converter (DAC) channels, each DAC channel including a DAC circuit connected to an input of an amplifier circuit;
a summing node connected to outputs of the amplifier circuits of the DAC channels to provide a system output;
a system memory; and
a control circuit operatively coupled to the DAC channels and the system output, wherein the control circuit is configured to:
sweep a DAC code of at least one DAC circuit of the DAC channels over a specified range of DAC code values;
store DAC glitch characteristic data for DAC code transitions in the system memory;
update the DAC circuits of the DAC channels with DAC codes to adjust the system output to a steady state target output in a steady state, wherein the DAC codes are selected from a first set of DAC codes;
detect when the DAC codes selected from the first set of DAC codes result in a glitch condition at outputs of the DAC circuits in the steady state including detecting a high glitch transition using the stored DAC glitch characteristic data; and
change to selecting the DAC codes from a second set of DAC codes that maintain the same steady state target output and reduce glitching at the outputs of the DAC circuits.

### Claim 19 (depends on 18)

The power supply system of claim 18, wherein the control circuit is configured to:
determine a control loop offset according to a glitch magnitude of the high-glitch DAC code transitions; and
add the control loop offset to the summing node to change to the selecting the DAC codes from the second set of DAC codes.