# US 12,763,780 B2 · Device and method for multi-chip clock synchronization

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- Number: US 12,763,780 B2
- Document ID: US12763780B2
- Status: Granted
- Kind: B2
- Application number: 18/518,733
- Filed: 2023-11-24
- Published: 2024-05-30
- Granted: 2026-10-13
- Earliest claimed: 2022-11-25
- Assignees: Lx Semicon Co., Ltd.
- Applicants: Lx Semicon Co., Ltd.
- Inventors: Jae Hwan Lee; Yoon Hoe Kim; Ji Hye Kim; Seung Chan Jung; Hyun Soo Chung
- Web page: https://patentgrep.com/patent/US12763780B2

## CPC

- H03L 7/083: the reference signal being additionally directly applied to the generator
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/1077: {by changing characteristics of the phase or frequency detection means (H03L7/1072 takes precedence)}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

The present disclosure relates to a multi-chip clock synchronization device and a method capable of reducing an operating frequency and power consumption when a plurality of chips share clocks for multi-chip clock synchronization, which may include a reference clock supply unit connected to a plurality of chips and supplying a reference clock of a first frequency to each chip and a target clock generation unit generating a target clock of a second frequency based on the reference clock of the first frequency, wherein the reference clock supply unit may generate the reference clock of the first frequency which is N times lower than the second frequency of the target clock to supply the generated reference clock to each chip, and the target clock generation unit may multiply the first frequency of the reference clock by N times when the reference clock of the first frequency is input to generate the target clock of the second frequency.

## Claims

### Claim 1

A multi-chip clock synchronization device comprising:
a reference clock supply unit connected to a plurality of chips and configured to supply a reference clock having a first frequency to each of the plurality of chips; and
a target clock generation unit configured to generate a target clock having a second frequency based on the reference clock of the first frequency, wherein
the reference clock supply unit is configured to generate the reference clock having the first frequency which is N times lower than the second frequency of the target clock to supply the generated reference clock to the each of the plurality of chips,
the target clock generation unit is configured to multiply the first frequency of the reference clock by N times when the reference clock of the first frequency is inputted to generate the target clock having the second frequency,
the reference clock supply unit is configured to determine the first frequency as a lowest frequency of the reference clock if a jitter is generated when the target clock generation unit multiplies the first frequency of the reference clock by N times, and
the reference clock supply unit is further configured to determine the first frequency of the reference clock to be low when a total number of the plurality of chips increases, thereby reducing power consumption due to clock transmission.

### Claim 2 (depends on 1)

The multi-chip clock synchronization device of claim 1, wherein
the reference clock supply unit is configured to generate the reference clock outside the plurality of chips such that the reference clock is supplied to the plurality of chips equally,
the target clock generation unit is individually disposed inside each of the plurality of chips, and
the target clock generation unit disposed inside each of the plurality of chips is configured to generate the target clock having the second frequency for each of the plurality of chips.

### Claim 3 (depends on 2)

The multi-chip clock synchronization device of claim 2, wherein the reference clock supply unit is configured to transmit the reference clock to the plurality of chips simultaneously.

### Claim 4 (depends on 2)

The multi-chip clock synchronization device of claim 2, wherein the reference clock supply unit is configured to supply the reference clock to each of the plurality of chips through a clock input terminal of each of the plurality of chips.

### Claim 5 (depends on 2)

The multi-chip clock synchronization device of claim 2, wherein the number of the target clock generation units disposed inside the plurality of chips is same as the number of plurality of chips.

### Claim 6 (depends on 2)

The multi-chip clock synchronization device of claim 2, wherein the target clock generation unit disposed in each of the plurality of chips is configured to generate the target clock having the second frequency using the following equation: F_SYS=F_REF×N where F_SYS is a target clock frequency of a system, F_REF is a reference clock frequency, and N is a natural number.

### Claim 7 (depends on 2)

The multi-chip clock synchronization device of claim 2, wherein the target clock generation unit disposed inside each of the plurality of chips includes:
a phase frequency detector configured to receive the reference clock and a clock multiplied by N times and detect a phase difference between the reference clock and the clock multiplied by N times;
a voltage control oscillator configured to control a phase of the clock multiplied by N times based on the phase difference detected by the phase frequency detector to output the target clock having the second frequency; and
a clock frequency multiplier configured to multiply a frequency of the clock whose phase is controlled by the voltage control oscillator by N times to feed back the clock multiplied by N times to the phase frequency detector.

### Claim 8 (depends on 7)

The multi-chip clock synchronization device of claim 7, wherein the target clock generation unit disposed inside each of the plurality of chips further includes a filter unit that is electrically connected between the phase frequency detector and the voltage control oscillator to remove noise from a clock signal.

### Claim 9 (depends on 2)

The multi-chip clock synchronization device of claim 2, wherein
a plurality of target clock generation units is disposed to correspond to each chip of the plurality of chips, and
the plurality of target clock generation units is configured to multiply the frequency of the target clock by the same multiple to generate the target clock of the same second frequency.

### Claim 10 (depends on 1)

The multi-chip clock synchronization device of claim 1, wherein
the plurality of chips includes a master chip and a plurality of slave chips,
the master chip includes the reference clock supply unit,
the master chip is configured to generate the reference clock and supply, through a clock output terminal of the master chip, the reference clock to the plurality of slave chips, and
the target clock generation unit is individually disposed inside each of the master chip and the plurality of slave chips and configured to generate the target clock having the second frequency for each of the plurality of chips.

### Claim 11 (depends on 10)

The multi-chip clock synchronization device of claim 10, wherein the reference clock supply unit includes:
a vibrator;
a vibrator driver configured to drive the vibrator to output a vibration frequency; and
a clock distribution part configured to divide the vibration frequency based on a preset division rate to generate the reference clock having the first frequency.

### Claim 12 (depends on 11)

The multi-chip clock synchronization device of claim 11, wherein the vibrator has one end connected to an input terminal of the master chip and the other end connected to an output terminal of the master chip.

### Claim 13 (depends on 11)

The multi-chip clock synchronization device of claim 11, wherein the clock distribution part is configured to generate the reference clock having the first frequency using the following equation: F_REF=F_XOCS/R, where F_REF is the first frequency, F_XOCS is the vibration frequency, and R is the division rate.

### Claim 14 (depends on 10)

The multi-chip clock synchronization device of claim 10, wherein
the reference clock supply unit is individually disposed inside each of the master chip and the plurality of slave chips,
the reference clock supply unit disposed inside the master chip is turned on to be activated so as to generate the reference clock, and
the reference clock supply unit disposed inside each of the plurality of slave chips is turned off to be inactivated so as not to generate the reference clock.

### Claim 15 (depends on 14)

The multi-chip clock synchronization device of claim 14, wherein
the reference clock supply unit of the master chip is configured to transmit the reference clock to a clock input terminal of each of the plurality of slave chips through a clock output terminal of the master chip, and
the reference clock inputted to each of the plurality of slave chips is inputted to the target clock generation unit disposed inside each of the plurality of slave chips.

### Claim 16 (depends on 10)

The multi-chip clock synchronization device of claim 10, wherein
the reference clock supply unit is individually disposed inside each of the master chip and the plurality of slave chips,
the reference clock supply unit disposed inside the master chip is turned on to be activated so as to generate the reference clock, and
the reference clock supply unit disposed inside each of the plurality of slave chips is turned off and is configured to buffer the reference clock inputted from the master chip to supply to the target clock generation unit.

### Claim 17 (depends on 16)

The multi-chip clock synchronization device of claim 16, wherein
the reference clock supply unit of the master chip transmits the reference clock to an input terminal for connecting a vibrator of each slave chip through the clock output terminal of the master chip, and
the reference clock is input to a vibrator driver for buffering the clock of the reference clock supply unit disposed inside the slave chip.

### Claim 18

A multi-chip clock synchronization method comprising:
generating a reference clock having a first frequency which is N times lower than a second frequency of a target clock;
supplying the reference clock having the first frequency to each of multiple chips;
generating the target clock having the second frequency by multiplying the first frequency of the reference clock in each of the multiple chips by N times when the reference clock of the first frequency is input to each chip; and
synchronizing clocks of the multiple chips based on a target clock having the second frequency;
wherein the first frequency is determined as a lowest frequency of the reference clock if a jitter is generated when the first frequency of the reference clock is multiplied by N times, and
wherein the first frequency of the reference clock is determined to be low when a total number of the plurality of chips increases, thereby reducing power consumption due to clock transmission.

### Claim 19

A display device comprising:
a touch panel in which a plurality of touch sensors is disposed;
a touch driving device configured to drive the plurality of touch sensors; and
a multi-chip clock synchronization device configured to apply a target clock to a plurality of chips of the touch driving device to synchronize clocks of the plurality of chips, wherein
the multi-chip clock synchronization device includes:
a reference clock supply unit connected to a plurality of chips and supplying a reference clock of a first frequency to each chip of the plurality of chips; and
a target clock generation unit configured to generate a target clock of a second frequency based on the reference clock of the first frequency input to each chip, wherein
the reference clock supply unit is configured to generate the reference clock of the first frequency which is N times lower than the second frequency of the target clock to supply the generated reference clock to each chip,
the target clock generation unit is configured to multiply the first frequency of the reference clock by N times when the reference clock of the first frequency is input to generate the target clock of the second frequency,
the reference clock supply unit is configured to determine the first frequency as a lowest frequency of the reference clock if a jitter is generated when the target clock generation unit multiplies the first frequency of the reference clock by N times, and
the reference clock supply unit is further configured to determine the first frequency of the reference clock to be low when a total number of the plurality of chips increases, thereby reducing power consumption due to clock transmission.

### Claim 20 (depends on 19)

The display device of claim 19, further comprising:
a display panel on which a plurality of pixels is disposed;
a data driving device configured to drive data lines connected to the plurality of pixels;
a gate driving device configured to drive gate lines connected to the plurality of pixels; and
a data processing device configured to transmit video data and a data control signal to the data driving device, wherein
the multi-chip clock synchronization device is configured to apply the target clock to a plurality of chips of at least one of the data driving device, the gate driving device, and the data processing device to synchronize clocks of the plurality of chips of said at least one of the data driving device, the gate driving device, and the data processing device.