# US 12,763,777 B2 · Audio restore circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,777 B2 - Document ID: US12763777B2 - Status: Granted - Kind: B2 - Application number: 18/424,856 - Filed: 2024-01-28 - Published: 2024-08-15 - Granted: 2026-10-13 - Earliest claimed: 2023-02-15 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corporation - Inventors: Chien-Hsun Lu; Yi-Han Peng - Web page: https://patentgrep.com/patent/US12763777B2 ## CPC - H03L 7/0814: {the phase shifting device being digitally controlled} - H04R 5/04: Circuit arrangements, {e.g. for selective connection of amplifier inputs/outputs to loudspeakers, for loudspeaker detection, or for adaptation of settings to personal preferences or hearing impairments (combinations of amplifiers H03F3/68; stereophonic systems H04S)} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H04R: LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS (producing sounds with frequency not determined by supply frequency G10K) ## Abstract An audio restore circuit includes an audio tracking circuit, a clock adjustment circuit, and an audio generator circuit. The audio tracking circuit is configured to generate a first control signal according to a sampling rate of an audio sampled signal and a clock rate of an audio clock signal. The clock adjustment circuit is configured to adjust the clock rate of the audio clock signal according to the first control signal. The audio generator circuit is configured to output a plurality of audio output signals according to the audio sampled signal and the audio clock signal. ## Claims ### Claim 1 An audio restore circuit, comprising: an audio tracking circuit configured to generate a first control signal according to a sampling rate of an audio sampled signal and a clock rate of an audio clock signal; a clock adjustment circuit configured to adjust the clock rate of the audio clock signal according to the first control signal; and an audio generator circuit configured to output a plurality of audio output signals according to the audio sampled signal and the audio clock signal, wherein the audio tracking circuit is further configured to generate a first flag signal according to the sampling rate of the audio sampled signal and a first counting threshold value, generate a second flag signal according to the clock rate of the audio clock signal and a second counting threshold value, generate a second control signal according to the first flag signal and the second flag signal, and generate the first control signal according to the second control signal. ### Claim 2 (depends on 1) The audio restore circuit of claim 1, wherein the first counting threshold value is greater than or equal to the second counting threshold value. ### Claim 3 (depends on 1) The audio restore circuit of claim 1, wherein the first counting threshold value and the second counting threshold value satisfy a formula below: A = C 2 × B wherein A is the first counting threshold value, B is the second counting threshold value, and C is a channel number corresponding to the plurality of audio output signals. ### Claim 4 (depends on 1) The audio restore circuit of claim 1, wherein the second control signal comprises an enable signal, wherein when a first flagging time point of the first flag signal is identical to a second flagging time point of the second flag signal, the audio tracking circuit generates the enable signal with a first logic value to maintain the clock rate of the audio clock signal, wherein when the first flagging time point is non-identical to the second flagging time point, the audio tracking circuit generates the enable signal with a second logic value to adjust the clock rate of the audio clock signal. ### Claim 5 (depends on 4) The audio restore circuit of claim 4, wherein the second control signal further comprises a speed-up signal and a slow-down signal, wherein when the first flagging time point is earlier than the second flagging time point, the audio tracking circuit generates the speed-up signal to speed up the clock rate, wherein when the first flagging time point is later than the second flagging time point, the audio tracking circuit generates the slow-down signal to slow down the clock rate. ### Claim 6 (depends on 1) The audio restore circuit of claim 1, wherein the audio generator circuit comprises: a storage circuit configured to receive and store a decoded audio sampled signal, wherein the audio tracking circuit is further configured to generate a third control signal according to a data amount in the storage circuit, a data water level upper limit of the storage circuit, and a data water level lower limit of the storage circuit, and generate the first control signal according to the third control signal and the second control signal. ### Claim 7 (depends on 6) The audio restore circuit of claim 6, wherein the storage circuit comprises a first-in first-out memory. ### Claim 8 (depends on 6) The audio restore circuit of claim 6, wherein the third control signal comprises an enable signal, wherein when the data amount is between the data water level upper limit and the data water level lower limit, the audio tracking circuit generates the enable signal with a first logic value to maintain the clock rate of the audio clock signal, wherein when the data amount is greater than the data water level upper limit or less than the data water level lower limit, the audio tracking circuit generates the enable signal with a second logic value to adjust the clock rate of the audio clock signal. ### Claim 9 (depends on 8) The audio restore circuit of claim 8, wherein the third control signal further comprises a speed-up signal and a slow-down signal, wherein when the data amount is greater than the data water level upper limit, the audio tracking circuit generates the speed-up signal to speed up the clock rate, wherein when the data amount is less than the data water level lower limit, the audio tracking circuit generates the slow-down signal to slow down the clock rate. ### Claim 10 (depends on 6) The audio restore circuit of claim 6, wherein the second control signal corresponds to a first weighting value, and the third control signal corresponds to a second weighting value. ### Claim 11 (depends on 10) The audio restore circuit of claim 10, wherein the audio tracking circuit comprises: a control circuit configured to generate the first control signal according to the second control signal, the third control signal, the first weighting value, and the second weighting value, and transmit the first control signal to the clock adjustment circuit to adjust the clock rate of the audio clock signal. ### Claim 12 (depends on 11) The audio restore circuit of claim 11, wherein the clock adjustment circuit comprises: a phase-locked loop circuit configured to generate a phase-locked loop clock signal; and a clock generator circuit configured to generate the audio clock signal according to the phase-locked loop clock signal. ### Claim 13 (depends on 1) The audio restore circuit of claim 1, wherein the plurality of audio output signals correspond to a plurality of audio channels. ### Claim 14 An audio restore circuit, comprising: an audio tracking circuit configured to generate an enable signal and one of a speed-up signal and a slow-down signal according to a data amount of an audio sampled signal, a data water level upper limit, and a data water level lower limit; a clock adjustment circuit configured to adjust a clock rate of an audio clock signal according to the enable signal and the one of the speed-up signal and the slow-down signal; and an audio generator circuit configured to output a plurality of audio output signals according to the audio sampled signal and the audio clock signal, wherein the audio generator circuit comprises: a storage circuit configured to receive and store the audio sampled signal. ### Claim 15 (depends on 14) The audio restore circuit of claim 14, wherein the storage circuit comprises a first-in first-out memory. ### Claim 16 (depends on 14) The audio restore circuit of claim 14, wherein when the data amount is between the data water level upper limit and the data water level lower limit, the audio tracking circuit generates the enable signal with a first logic value to maintain the clock rate of the audio clock signal, wherein when the data amount is greater than the data water level upper limit or less than the data water level lower limit, the audio tracking circuit generates the enable signal with a second logic value to adjust the clock rate of the audio clock signal. ### Claim 17 (depends on 16) The audio restore circuit of claim 16, wherein when the data amount is greater than the data water level upper limit, the audio tracking circuit generates the speed-up signal to speed up the clock rate, wherein when the data amount is less than the data water level lower limit, the audio tracking circuit generates the slow-down signal to slow down the clock rate. ### Claim 18 (depends on 14) The audio restore circuit of claim 14, wherein the plurality of audio output signals correspond to a plurality of audio channels.