# US 12,763,776 B1 · Level shifting circuit with integrated latch > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,776 B1 - Document ID: US12763776B1 - Status: Granted - Kind: B1 - Application number: 19/174,981 - Filed: 2025-04-10 - Published: 2026-10-15 - Granted: 2026-10-13 - Earliest claimed: 2025-04-10 - Assignees: M31 Technology Corporation - Applicants: M31 Technology Corporation - Inventors: Saikat Kumar Banik; Anoop Delampady - Web page: https://patentgrep.com/patent/US12763776B1 ## CPC - H03K 19/018528: {with at least one differential stage} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A level shifting circuit includes a front stage and a rear stage. The front stage and the rear stage are operated according to a first clock and a second clock. During a first phase of the first clock, the front stage is in a conversion mode, the rear stage is in a propagation mode, and the front stage is served as a level shifter. Furthermore, the input signal between a first supply voltage and a ground voltage is converted into a shifted signal between a second supply voltage and the ground voltage. During a second phase of the first clock, the front stage is in a tri-state output mode, the rear stage is in a retention mode, and the rear stage is served as a latch. Furthermore, the output signal from the rear stage is maintained at a specified logic level. ## Claims ### Claim 1 A level shifting circuit with an integrated latch, the level shifting circuit comprising: a front stage, wherein an input terminal of the front stage is arranged to receive an input signal, a first clock terminal of the front stage is arranged to receive a first clock, a second clock terminal of the front stage is arranged to receive a second clock, wherein the first clock and the second clock are complementary to each other, the first clock is at a first level during a first phase, and the first clock is at a second level during a second phase; a rear stage, wherein an input terminal of the rear stage is connected to an output terminal of the front stage, a first clock terminal of the rear stage is arranged to receive the first clock, a second clock terminal of the rear stage is arranged to receive the second clock, and an output terminal of the rear stage is arranged to generate an output signal, wherein during the first phase, the front stage is in a conversion mode, the rear stage is in a propagation mode, and the front stage serves as a level shifter, wherein the input signal in a range between a first supply voltage and a ground voltage is converted into a shifted signal in a range between a second supply voltage and the ground voltage by the front stage, and the rear stage is configured to receive the shifted signal and generate the output signal, wherein the first supply voltage is lower than the second supply voltage, wherein during the second phase, the front stage is in a tri-state output mode, the rear stage is in a retention mode, and the rear stage serves as a latch, wherein the output terminal of the front stage has a high output impedance, and the output signal from the rear stage is maintained at a specified logic level and kept unchanged. ### Claim 2 (depends on 1) The level shifting circuit as claimed in claim 1, wherein when a logic level of the input signal is subjected to a change during the first phase, the logic level of the output signal is correspondingly changed, wherein when the logic level of the input signal is subjected to the change during the second phase, the output signal is maintained at the specified logic level and kept unchanged. ### Claim 3 (depends on 1) The level shifting circuit as claimed in claim 1, wherein the front stage comprises: a header switch, wherein a first terminal of the header switch is arranged to receive the second supply voltage, a second terminal of the header switch is connected to a first node, and a control terminal of the header switch is arranged to receive the first clock; a footer switch, wherein a first terminal of the footer switch is connected to a second node, a second terminal of the footer switch is arranged to receive the ground voltage, and a control terminal of the footer switch is arranged to receive the second clock; and a converter, wherein a first power terminal of the converter is connected to the first node, a second power terminal of the converter is connected to the second node, a first input terminal of the converter is arranged to receive the input signal, and a second input terminal of the converter is arranged to receive an inverted signal of the input signal, wherein during the first phase, the shifted signal is outputted from an output terminal of the converter, and the input signal in the range between the first supply voltage and the ground voltage is converted into the shifted signal in the range between the second supply voltage and the ground voltage by the converter, wherein during the second phase, the output terminal of the converter has the high output impedance. ### Claim 4 (depends on 3) The level shifting circuit as claimed in claim 3, wherein the header switch comprises a first transistor, wherein a first terminal of the first transistor is arranged to receive the second supply voltage, a second terminal of the first transistor is connected to the first node, and a control terminal of the first transistor is arranged to receive the first clock. ### Claim 5 (depends on 4) The level shifting circuit as claimed in claim 4, wherein the footer switch comprises a second transistor, wherein a first terminal of the second transistor is connected to the second node, a second terminal of the second transistor is arranged to receive the ground voltage, and a control terminal of the second transistor is arranged to receive the second clock. ### Claim 6 (depends on 3) The level shifting circuit as claimed in claim 3, wherein the converter comprises: a first transistor, wherein a first terminal of the first transistor is connected to a third node, a second terminal of the first transistor is connected to the second node, and a control terminal of the first transistor is arranged to receive the input signal; a second transistor, wherein a first terminal of the second transistor is connected to a fourth node, a second terminal of the second transistor is connected to the second node, and a control terminal of the second transistor is arranged to receive the inverted signal; a third transistor, wherein a first terminal of the third transistor is connected to the first node, a second terminal of the third transistor is connected to the third node, and a control terminal of the third transistor is connected to the fourth node; and a fourth transistor, wherein a first terminal of the fourth transistor is connected to the first node, a second terminal of the fourth transistor is connected to the fourth node, and a control terminal of the fourth transistor is connected to the third node, wherein the third node is the output terminal of the front stage. ### Claim 7 (depends on 3) The level shifting circuit as claimed in claim 3, wherein the header switch comprises: a first transistor, wherein a first terminal of the first transistor is arranged to receive the second supply voltage, a second terminal of the first transistor is connected to the first node, and a control terminal of the first transistor is arranged to receive the first clock; and a second transistor, wherein a first terminal of the second transistor is arranged to receive the second supply voltage, a second terminal of the second transistor is connected to the first node, and a control terminal of the second transistor is arranged to receive the second clock, wherein the first transistor and the second transistor are configured to collaboratively operate as a first transmission gate. ### Claim 8 (depends on 7) The level shifting circuit as claimed in claim 7, wherein the footer switch comprises: a third transistor, wherein a first terminal of the third transistor is connected to the second node, a second terminal of the third transistor is arranged to receive the ground voltage, and a control terminal of the third transistor is arranged to receive the first clock; and a fourth transistor, wherein a first terminal of the fourth transistor is connected to the second node, a second terminal of the fourth transistor is arranged to receive the ground voltage, and a control terminal of the fourth transistor is arranged to receive the second clock, wherein the third transistor and the fourth transistor are configured to collaboratively operate as a second transmission gate. ### Claim 9 (depends on 3) The level shifting circuit as claimed in claim 3, wherein the converter comprises: a first transistor, wherein a first terminal of the first transistor is connected to a third node, a second terminal of the first transistor is connected to the second node, and a control terminal of the first transistor is arranged to receive the input signal; a second transistor, wherein a first terminal of the second transistor is connected to a fourth node, a second terminal of the second transistor is connected to the second node, and a control terminal of the second transistor is arranged to receive the inverted signal; a third transistor, wherein a first terminal of the third transistor is connected to the first node, and a control terminal of the third transistor is connected to the fourth node; a fourth transistor, wherein a first terminal of the fourth transistor is connected to a second terminal of the third transistor, a second terminal of the fourth transistor is connected to the third node, and a control terminal of the fourth transistor is arranged to receive the input signal; a fifth transistor, wherein a first terminal of the fifth transistor is connected to the first node, and a control terminal of the fifth transistor is connected to the third node; and a sixth transistor, wherein a first terminal of the sixth transistor is connected to a second terminal of the fifth transistor, a second terminal of the sixth transistor is connected to the fourth node, and a control terminal of the sixth transistor is arranged to receive the inverted signal, wherein the third node is the output terminal of the front stage. ### Claim 10 (depends on 3) The level shifting circuit as claimed in claim 3, further comprising: an inverter, wherein a first power terminal of the inverter is arranged to receive the first supply voltage, a second power terminal of the inverter is arranged to receive the ground voltage, an input terminal of the inverter is arranged to receive the input signal, and an output terminal of the inverter is arranged to generate the inverted signal. ### Claim 11 (depends on 1) The level shifting circuit as claimed in claim 1, wherein the rear stage comprises: a first inverter, wherein a first power terminal of the first inverter is arranged to receive the second supply voltage, a second power terminal of the first inverter is arranged to receive the ground voltage, an input terminal of the first inverter is connected to the output terminal of the front stage, and an output terminal of the first inverter is arranged to generate the output signal; a second inverter, wherein a first power terminal of the second inverter is arranged to receive the second supply voltage, a second power terminal of the second inverter is arranged to receive the ground voltage, and an input terminal of the second inverter is connected to the output terminal of the first inverter; and a transmission gate, wherein a first terminal of the transmission gate is connected to an output terminal of the second inverter, a second terminal of the transmission gate is connected to the input terminal of the first inverter, a first clock terminal of the transmission gate is arranged to receive the first clock, and a second clock terminal of the transmission gate is arranged to receive the second clock, wherein during the first phase, the transmission gate is turned off, and the first inverter is arranged to generate the output signal according to the shifted signal, wherein during the second phase, the transmission gate is turned on, and the first inverter and the second inverter are configured to collaboratively operate as the latch. ### Claim 12 (depends on 11) The level shifting circuit as claimed in claim 11, wherein the transmission gate comprises: a first transistor, wherein a first terminal of the first transistor is connected to the output terminal of the second inverter, a second terminal of the first transistor is connected to the input terminal of the first inverter, and a control terminal of the first transistor is arranged to receive the first clock; and a second transistor, wherein a first terminal of the second transistor is connected to the output terminal of the second inverter, a second terminal of the second transistor is connected to the input terminal of the first inverter, and a control terminal of the second transistor is arranged to receive the second clock. ### Claim 13 (depends on 1) The level shifting circuit as claimed in claim 1, wherein the rear stage comprises: an inverter, wherein a first power terminal of the inverter is arranged to receive the second supply voltage, a second power terminal of the inverter is arranged to receive the ground voltage, an input terminal of the inverter is connected to the output terminal of the front stage, and an output terminal of the inverter is arranged to generate the output signal; a header switch, wherein a first terminal of the header switch is arranged to receive the second supply voltage, a second terminal of the header switch is connected to a first node, and a control terminal of the header switch is arranged to receive the second clock; a footer switch, wherein a first terminal of the footer switch is connected to a second node, a second terminal of the footer switch is arranged to receive the ground voltage, and a control terminal of the footer switch is arranged to receive the first clock; a first transistor, wherein a first terminal of the first transistor is connected to the first node, a second terminal of the first transistor is connected to the input terminal of the inverter, and a control terminal of the first transistor is connected to the output terminal of the inverter; and a second transistor, wherein a first terminal of the second transistor is connected to the input terminal of the inverter, a second terminal of the second transistor is connected to the second node, and a control terminal of the second transistor is connected to the output terminal of the inverter, wherein during the first phase, the header switch and the footer switch are turned off, and the inverter is arranged to generate the output signal according to the shifted signal, wherein during the second phase, the header switch and the footer switch are turned on, and the rear stage is configured to operate as the latch. ### Claim 14 (depends on 13) The level shifting circuit as claimed in claim 13, wherein the header switch comprises a third transistor, wherein a first terminal of the third transistor is arranged to receive the second supply voltage, a second terminal of the third transistor is connected to the first node, and a control terminal of the third transistor is arranged to receive the second clock. ### Claim 15 (depends on 14) The level shifting circuit as claimed in claim 14, wherein the footer switch comprises a fourth transistor, wherein a first terminal of the fourth transistor is connected to the second node, a second terminal of the fourth transistor is arranged to receive the ground voltage, and a control terminal of the fourth transistor is arranged to receive the first clock. ### Claim 16 (depends on 13) The level shifting circuit as claimed in claim 13, wherein the header switch comprises: a third transistor, wherein a first terminal of the third transistor is arranged to receive the second supply voltage, a second terminal of the third transistor is connected to the first node, and a control terminal of the third transistor is arranged to receive the first clock; and a fourth transistor, wherein a first terminal of the fourth transistor is arranged to receive the second supply voltage, a second terminal of the fourth transistor is connected to the first node, and a control terminal of the fourth transistor is arranged to receive the second clock, wherein the third transistor and the fourth transistor are configured to collaboratively operate as a first transmission gate. ### Claim 17 (depends on 16) The level shifting circuit as claimed in claim 16, wherein the footer switch comprises: a fifth transistor, wherein a first terminal of the fifth transistor is connected to the second node, a second terminal of the fifth transistor is arranged to receive the ground voltage, and a control terminal of the fifth transistor is arranged to receive the first clock; and a sixth transistor, wherein a first terminal of the sixth transistor is connected to the second node, a second terminal of the sixth transistor is arranged to receive the ground voltage, and a control terminal of the sixth transistor is arranged to receive the second clock, wherein the fifth transistor and the sixth transistor are configured to collaboratively operate as a second transmission gate.