# US 12,763,774 B2 · Apparatus including a CMOS pass gate circuit and a bootstrap circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,774 B2 - Document ID: US12763774B2 - Status: Granted - Kind: B2 - Application number: 18/760,689 - Filed: 2024-07-01 - Published: 2025-10-02 - Granted: 2026-10-13 - Earliest claimed: 2024-04-01 - Assignees: Microsemi SoC Corporation - Applicants: Microsemi SoC Corp. - Inventors: John Lynn McCollum; Fethi Dhaoui - Web page: https://patentgrep.com/patent/US12763774B2 ## CPC - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 17/063: {in field-effect transistor switches} - H03K 19/01714: {by bootstrapping, i.e. by positive feed-back} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract One or more examples relate to a complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit includes an n-channel transistor and a p-channel transistor. The control circuit may activate and deactivate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control circuit. The bootstrap circuit may increase a first drive gain of the n-channel transistor and a second drive gain of the p-channel transistor. ## Claims ### Claim 1 An apparatus comprising: a complementary metal-oxide-semiconductor (CMOS) pass gate circuit including a first n-channel transistor and a first p-channel transistor; a control circuit to generate control signals to activate the CMOS pass gate circuit; a bootstrap circuit electrically connected between the CMOS pass gate circuit and the control circuit, said bootstrap circuit to increase a first drive gain of the first n-channel transistor and a second drive gain of the first p-channel transistor; and an input terminal electrically connected to the CMOS pass gate circuit, said input terminal to convey an input signal to the CMOS pass gate circuit, said input signal to alternate between a high voltage level and a low voltage level, said high voltage level being greater than said low voltage level, wherein said bootstrap circuit comprises a second n-channel transistor and a second p-channel transistor, said second n-channel transistor electrically connected between the control circuit and the first n-channel transistor, said second p-channel transistor electrically connected between the control circuit and the first p-channel transistor, said second n-channel transistor to receive a first complementary control signal of the control signals and convey a first drive voltage corresponding to the first complementary control signal to the first n-channel transistor, said first drive voltage to activate the first n-channel transistor and increase the first drive gain, said second p-channel transistor to receive a second complementary control signal of the control signals and convey a second drive voltage corresponding to the second complementary control signal to the first p-channel transistor, said second drive voltage to activate the first p-channel transistor and increase the second drive gain, respective ones of said first p-channel transistor, first n-channel transistor, second p-channel transistor, and second n-channel transistor including a respective gate terminal, a respective source terminal, and a respective drain terminal, a first capacitive coupling being formed between the gate and source terminals of the first n-channel transistor, said first capacitive coupling generated by the first drive voltage, a second capacitive coupling being formed between the gate and source terminals of the first p-channel transistor, said second capacitive coupling generated by the second drive voltage. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein said control circuit including an output having a first signal path electrically connected to the second p-channel transistor and a second signal path electrically connected to the second n-channel transistor, said second signal path including an inverter, said inverter to invert a control signal of the control signals to generate the first complementary control signal. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein said control circuit includes a first output electrically connected to the second n-channel transistor and a second output electrically connected to the second p-channel transistor, said first output to convey the first complementary control signal to the second n-channel transistor, said second output to convey the second complementary control signal to the second p-channel transistor. ### Claim 4 (depends on 1) The apparatus of claim 1, said first and second capacitive couplings to increase a first gate voltage of the first n-channel transistor and a second gate voltage of the first p-channel transistor in proportion to a rise of the input signal. ### Claim 5 (depends on 1) The apparatus of claim 1, said first and second capacitive couplings to decrease a first gate voltage of the first n-channel transistor and a second gate voltage of the first p-channel transistor in proportion to a fall of the input signal. ### Claim 6 (depends on 1) The apparatus of claim 1, including said gate terminal of the first p-channel transistor electrically connected to the source terminal of the second p-channel transistor, said gate terminal of the first n-channel transistor electrically connected to the source terminal of the second n-channel transistor, said source terminals of the first p-channel transistor and the first n-channel transistor electrically connected to the input terminal, said gate terminals of the second p-channel transistor and the second n-channel transistor electrically connected to one or more power supplies, said drain terminals of the second p-channel transistor and the second n-channel transistor electrically connected to the control circuit. ### Claim 7 (depends on 1) The apparatus of claim 1, comprising a first gate-source voltage of the first n-channel transistor to have a first constant voltage value maintained by said first capacitive coupling, a second gate-source voltage of the first p-channel transistor to have a second constant voltage value maintained by said second capacitive coupling. ### Claim 8 (depends on 7) The apparatus of claim 7, said first constant voltage value being maintained at a source voltage Vdd, said second constant voltage value being maintained at a negative source voltage −Vdd. ### Claim 9 (depends on 1) The apparatus of claim 1, said first and second capacitive couplings being responsive to respective charge trapping at the gate terminals of the first n-channel transistor and the first p-channel transistor, said charge trapping being formed by a shutoff condition of the second n-channel transistor and the second p-channel transistor of the bootstrap circuit. ### Claim 10 A circuit arrangement comprising: a complementary metal-oxide-semiconductor (CMOS) pass gate circuit including a first n-channel transistor and a first p-channel transistor; a bootstrap circuit electrically connected to the CMOS pass gate circuit, said bootstrap circuit to increase a drive gain of the CMOS pass gate circuit; and an input terminal to receive an input signal, said input terminal electrically connected to the respective source terminals of the first n-channel transistor and the first p-channel transistor, wherein said bootstrap circuit comprises a second n-channel transistor electrically connected to the first n-channel transistor and a second p-channel transistor electrically connected to the first p-channel transistor, said second n-channel transistor to convey a first drive voltage to the first n-channel transistor, said second p-channel transistor to convey a second drive voltage to the first p-channel transistor, respective ones of said first p-channel transistor, first n-channel transistor, second p-channel transistor, and second n-channel transistor including a respective gate terminal, a respective source terminal, and a respective drain terminal, a first capacitive coupling being formed between the gate and source terminals of the first n-channel transistor, said first capacitive coupling generated by the first drive voltage, a second capacitive coupling being formed between the gate and source terminals of the first p-channel transistor, said second capacitive coupling generated by the second drive voltage. ### Claim 11 (depends on 10) The circuit arrangement of claim 10, comprising a first gate-source voltage of the first n-channel transistor to have a first constant voltage value maintained by said first capacitive coupling, a second gate-source voltage of the first p-channel transistor to have a second constant voltage value maintained by said second capacitive coupling. ### Claim 12 (depends on 11) The circuit arrangement of claim 11, said first constant voltage value being maintained at a source voltage Vdd, said second constant voltage value being maintained at a negative source voltage −Vdd. ### Claim 13 (depends on 10) The circuit arrangement of claim 10, comprising a control circuit, said gate terminal of the first p-channel transistor electrically connected to the source terminal of the second p-channel transistor, said gate terminal of the first n-channel transistor electrically connected to the source terminal of the second n-channel transistor, said source terminals of the first p-channel transistor and the first n-channel transistor electrically connected to the input terminal, said gate terminals of the second p-channel transistor and the second n-channel transistor electrically connected to one or more power supplies, said drain terminals of the second p-channel transistor and the second n-channel transistor electrically connected to the control circuit. ### Claim 14 (depends on 13) The circuit arrangement of claim 13, said control circuit to generate a control signal to activate the CMOS pass gate circuit, wherein said control circuit includes an output having a first signal path electrically connected to the second p-channel transistor and a second signal path electrically connected to the second n-channel transistor, said second signal path includes an inverter, said inverter to invert the control signal to generate a first complementary control signal. ### Claim 15 (depends on 13) The circuit arrangement of claim 13, said control circuit to generate control signals to activate the CMOS pass gate circuit, wherein said control signals include a first complementary control signal and a second complementary control signal, said control circuit includes a first output electrically connected to the second n-channel transistor and a second output electrically connected to the second p-channel transistor, said first output to convey the first complementary control signal to the second n-channel transistor, said second output to convey the second complementary control signal to the second p-channel transistor. ### Claim 16 (depends on 10) The circuit arrangement of claim 10, said first and second capacitive couplings being responsive to respective charge trapping at the gate terminals of the first n-channel transistor and the first p-channel transistor, said charge trapping being formed by a shutoff condition of the second n-channel transistor and the second p-channel transistor of the bootstrap circuit. ### Claim 17 A method comprising: activating, by one or more power supplies, a bootstrap circuit; generating, by a control circuit, one or more control signals; activating, by the bootstrap circuit, a complementary metal-oxide-semiconductor (CMOS) pass gate circuit based on the one or more control signals; receiving, by the CMOS pass gate circuit, an input signal; increasing, by the bootstrap circuit, a drive gain of the CMOS pass gate circuit; receiving, by a first n-channel transistor of the CMOS pass gate circuit, a first drive voltage corresponding to a first complementary control signal of the one or more control signals from the bootstrap circuit; receiving, by a first p-channel transistor of the CMOS pass gate circuit, a second drive voltage corresponding to a second complementary control signal of the one or more control signals from the bootstrap circuit; generating, in response to receiving the first drive voltage at the first n-channel transistor, a first capacitive coupling between a gate terminal and a source terminal of the first n-channel transistor, and generating, in response to receiving the second drive voltage at the first p-channel transistor, a second capacitive coupling between a gate terminal and a source terminal of the first p-channel transistor. ### Claim 18 (depends on 5) The method of claim 5, wherein increasing the drive gain of the CMOS pass gate circuit comprises increasing, by the first capacitive coupling, a first gate voltage of the first n-channel transistor in response to a rise in the input signal, decreasing, by the second capacitive coupling, a second gate voltage of the first p-channel transistor in response to a fall in the input signal. ### Claim 19 (depends on 5) The method of claim 5, said input signal increasing in voltage during a rise period and decreasing in voltage during a fall period, said increasing of the drive gain of the CMOS pass gate circuit including maintaining, by the first capacitive coupling, a first constant voltage value of a first gate-source voltage of the first n-channel transistor during the rise period and the fall period, maintaining, by the second capacitive coupling, a second constant voltage value of a second gate-source voltage of the first p-channel transistor during the rise period and the fall period. ### Claim 20 (depends on 19) The method of claim 19, said first constant voltage value being maintained at a source voltage Vdd, said second constant voltage value being maintained at a negative source voltage −Vdd.