# US 12,763,773 B2 · Aging resilient level shifter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,773 B2 - Document ID: US12763773B2 - Status: Granted - Kind: B2 - Application number: 18/442,632 - Filed: 2024-02-15 - Published: 2025-08-21 - Granted: 2026-10-13 - Earliest claimed: 2024-02-15 - Assignees: Silicon Laboratories Inc. - Applicants: Silicon Laboratories Inc. - Inventors: Håkon Børli; Pio Balmelli - Web page: https://patentgrep.com/patent/US12763773B2 ## CPC - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K 3/356113: {using additional transistors in the input circuit} - H03K 3/356182: {with additional means for controlling the main nodes} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An aging resilient level shifter has an increased lifetime as compared to a conventional level shifter. In at least one embodiment, a method for level-shifting a received signal from a first voltage domain to a second voltage domain includes controlling a cross-coupled pair of transistors according to an input signal and a complementary input signal to generate a signal on a pair of complementary nodes. The cross-coupled pair of transistors has a first doping type and the controlling uses a pair of transistors having a second doping type. The second doping type is complementary to the first doping type. The method includes isolating the pair of transistors from the pair of complementary nodes using a pair of isolation transistors and a pair of cascode transistors. The pair of cascode transistors is coupled between the pair of transistors and the pair of complementary nodes. ## Claims ### Claim 1 A method for level-shifting an input signal from a first voltage domain to an output signal of a second voltage domain, the method comprising: controlling a cross-coupled pair of transistors according to the input signal and a complementary input signal to generate a signal on a pair of complementary nodes, the cross-coupled pair of transistors having a first doping type and the controlling using a pair of transistors having a second doping type, the second doping type being complementary to the first doping type; isolating the pair of transistors from the pair of complementary nodes using a pair of isolation transistors and a pair of cascode transistors, the pair of isolation transistors and the pair of cascode transistors being coupled between the pair of transistors and the pair of complementary nodes; and biasing the pair of cascode transistors using a predetermined bias voltage, wherein the pair of isolation transistors is selectively disabled by an isolation control signal, wherein the first voltage domain has an input power supply voltage level above an input ground and the second voltage domain has an output power supply voltage level above an output ground, the output power supply voltage level being greater than the input power supply voltage level, and wherein the predetermined bias voltage is less than the output power supply voltage level and the predetermined bias voltage is greater than the input power supply voltage level. ### Claim 2 (depends on 1) The method as recited in claim 1 wherein the pair of transistors comprises low-voltage transistors, and wherein the cross-coupled pair of transistors, the pair of isolation transistors, and the pair of cascode transistors comprise high-voltage transistors. ### Claim 3 (depends on 1) The method as recited in claim 1 wherein the pair of transistors are in the first voltage domain, and wherein the cross-coupled pair of transistors, the pair of cascode transistors, and the pair of isolation transistors are in the second voltage domain. ### Claim 4 (depends on 1) The method as recited in claim 1 wherein the pair of isolation transistors reduce stress on the pair of cascode transistors. ### Claim 5 (depends on 1) The method as recited in claim 1 further comprising: receiving the input signal in the first voltage domain; and generating the complementary input signal based on the input signal in the first voltage domain, wherein the input signal and the complementary input signal have a first voltage swing between the input power supply voltage level and the input ground. ### Claim 6 (depends on 5) The method as recited in claim 5 further comprising: buffering the signal on the pair of complementary nodes in the second voltage domain to generate the output signal, wherein the output signal has a second voltage swing between the output power supply voltage level and the output ground, wherein the receiving and generating uses low-voltage transistors, and wherein the buffering uses high-voltage transistors. ### Claim 7 (depends on 1) The method as recited in claim 1 wherein the pair of isolation transistors is configured as a second pair of cascode transistors with respect to the pair of cascode transistors, thereby reducing stress on the pair of cascode transistors. ### Claim 8 (depends on 1) The method as recited in claim 1 wherein the isolation control signal is coupled to gate nodes of the pair of isolation transistors and the method further comprises: using the isolation control signal to disable the pair of isolation transistors; and while the pair of isolation transistors is disabled, forcing the pair of complementary nodes to a predetermined state in response to a second control signal. ### Claim 9 A level shifter comprising: a cross-coupled pair of transistors coupled between a first power supply node and a first pair of nodes, the cross-coupled pair of transistors having a first doping type; a pair of isolation transistors coupled between the first pair of nodes and a second pair of nodes, the pair of isolation transistors having a second doping type, the second doping type being complementary to the first doping type, wherein the pair of isolation transistors is selectively disabled by an isolation control signal; a pair of cascode transistors coupled between the second pair of nodes and a third pair of nodes, the pair of cascode transistors having the second doping type and being configured to receive a predetermined bias voltage; and a pair of transistors coupled between the third pair of nodes and a second power supply node, the pair of transistors having the second doping type, the pair of transistors being configured to receive an input signal and a complementary input signal, wherein the first power supply node is configured to receive an output power supply voltage level above an output ground and a third power supply node is configured to receive an input power supply voltage level above an input ground, the output power supply voltage level being greater than the input power supply voltage level, the second power supply node being coupled to the input ground, and wherein the predetermined bias voltage is less than the output power supply voltage level and the predetermined bias voltage is greater than the input power supply voltage level. ### Claim 10 (depends on 9) The level shifter as recited in claim 9 further comprising: an input circuit coupled between the second power supply node and the third power supply node and configured to generate the complementary input signal based on the input signal. ### Claim 11 (depends on 10) The level shifter as recited in claim 10 further comprising: an output circuit coupled between the first power supply node and a fourth power supply node and configured to generate an output signal on an output node based on a signal on the first pair of nodes. ### Claim 12 (depends on 11) The level shifter as recited in claim 11 wherein the input circuit receives the input signal, the input signal having a first voltage swing between the input power supply voltage level on the third power supply node and the input ground on the second power supply node, wherein the output signal has a second voltage swing between the output power supply voltage level on the first power supply node and the output ground on the fourth power supply node, and wherein the input power supply voltage level is less than the output power supply voltage level. ### Claim 13 (depends on 11) The level shifter as recited in claim 11 wherein the pair of transistors and the input circuit comprise low-voltage transistors; and wherein the output circuit, the cross-coupled pair of transistors, the pair of isolation transistors, and the pair of cascode transistors comprise high-voltage transistors. ### Claim 14 (depends on 11) The level shifter as recited in claim 11 wherein the input circuit and the pair of transistors are in a first voltage domain, and wherein the cross-coupled pair of transistors, the pair of isolation transistors, the pair of cascode transistors, and the output circuit are in a second voltage domain. ### Claim 15 (depends on 9) The level shifter as recited in claim 9 wherein the pair of isolation transistors is configured as a second pair of cascode transistors with respect to the pair of cascode transistors, thereby reducing stress on the pair of cascode transistors. ### Claim 16 A level shifter comprising: a first circuit comprising low-voltage transistors, the first circuit being coupled between a pair of complementary nodes and a first ground, and the first circuit being responsive to an input signal and a complementary input signal generated in a first voltage domain; and a second circuit comprising high-voltage transistors, the second circuit being coupled between the pair of complementary nodes and an output power supply node in a second voltage domain, wherein the second circuit further comprises: a cross-coupled pair of transistors coupled between the output power supply node and a second pair of complementary nodes, the cross-coupled pair of transistors having a first doping type; a pair of isolation transistors coupled between the second pair of complementary nodes and the pair of complementary nodes, the pair of isolation transistors having a second doping type and being selectively disabled by an isolation control signal; and a pair of cascode transistors coupled between the second pair of complementary nodes and the first ground, the pair of cascode transistors being configured to receive a predetermined bias voltage, wherein the predetermined bias voltage is less than an output power supply voltage on the output power supply node and the predetermined bias voltage is greater than an input power supply voltage level. ### Claim 17 (depends on 16) The level shifter as recited in claim 16 further comprising: an input buffer circuit comprising second low-voltage transistors coupled between an input power supply node and the first ground and configured to generate the complementary input signal based on the input signal generated in the first voltage domain; and an output circuit comprising second high-voltage transistors coupled between the output power supply node and an output ground and responsive to a signal on a node of the second pair of complementary nodes to generate an output signal in the second voltage domain. ### Claim 18 (depends on 16) The level shifter as recited in claim 16 wherein the second circuit further comprises: a second pair of cascode transistors coupled between a third pair of complementary nodes and the second pair of complementary nodes, the second pair of cascode transistors having the first doping type. ### Claim 19 (depends on 16) The level shifter as recited in claim 16 wherein the pair of isolation transistors is configured as a third pair of cascode transistors with respect to the pair of cascode transistors, thereby reducing stress on the pair of cascode transistors.