# US 12,763,771 B2 · Multiple or single voltage domain logic gate circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,771 B2 - Document ID: US12763771B2 - Status: Granted - Kind: B2 - Application number: 18/789,475 - Filed: 2024-07-30 - Published: 2026-02-05 - Granted: 2026-10-13 - Earliest claimed: 2024-07-30 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Mohit Chanana; Andy Wangkun Chen; Yew Keong Chong; Vivek Asthana; Himanshu Rathore; Abhishek Kumar - Web page: https://patentgrep.com/patent/US12763771B2 ## CPC - H03K 19/017509: {Interface arrangements} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuits comprising Boolean logic gate circuitry and corresponding voltage level shifting circuitry. ## Claims ### Claim 1 A circuit, comprising: a first logic gate circuit to implement a first type of Boolean function and comprising a first input terminal connected to an input signal line and a first output terminal connected to an output signal line, wherein the input signal line is in a first voltage domain and the output signal line is in a second voltage domain, the first logic gate circuit comprising; a first logic function circuit coupled to the input signal line and further coupled between the first output terminal and a reference voltage; and a second logic function circuit coupled to the input signal line and further complementary to the first logic function circuit and coupled between the first output terminal and a first header transistor; a second logic gate circuit to implement a second type of Boolean function and comprising a second input terminal connected to the input signal line and a second output terminal connected to a header control signal line, wherein the second type of Boolean function is a complementary type to the first type of Boolean function, the second logic gate circuit comprising; a third logic function circuit coupled to the input signal line and further coupled between the second output terminal and the reference voltage, the third logic function circuit identical to the first logic function circuit; and a fourth logic function circuit coupled to the input signal line and further complementary to the third logic function circuit and coupled between the second output terminal and a second voltage rail, the fourth logic function circuit identical to the second logic function circuit; the first header transistor to switchably couple an output voltage rail to the first logic gate circuit via a first header gate connected to the header control signal line, wherein the output voltage rail is in the second voltage domain; and a second header transistor to switchably couple the output voltage rail to the second logic gate circuit via a second header gate connected to the output signal line. ### Claim 2 (depends on 1) The circuit of claim 1, wherein: the first logic gate circuit comprises a first plurality of input terminals connected to a corresponding plurality of input signal lines, the first plurality of input terminals including the first input terminal; and the second logic gate circuit comprises a second plurality of input terminals connected to a corresponding subset of the plurality of input signal lines. ### Claim 3 (depends on 2) The circuit of claim 2, wherein an input connected to a signal line distinct from the corresponding subset of the plurality of input signal lines comprises an input transistor connected to the output voltage rail in parallel to the first header transistor. ### Claim 4 (depends on 3) The circuit of claim 3, further comprising a bypass transistor comprising a bypass gate connected to a bypass signal line, the bypass transistor connected to the second header transistor to decouple the second header transistor from the second logic gate circuit based on a bypass signal received via the bypass signal line. ### Claim 5 (depends on 4) The circuit of claim 4, further comprising: a second bypass transistor comprising a second bypass gate connected to the bypass signal line, the second bypass transistor connected to the second logic gate circuit and a low voltage (Vss) rail to couple the header control signal line to the Vss rail based at least in part on the bypass signal. ### Claim 6 (depends on 1) The circuit of claim 1, wherein the second logic gate circuit comprises: a third logic gate circuit to implement the first type of function and comprising the second input terminal and a third output terminal; and an inverter circuit comprising the second output terminal and an inverter input terminal connected to the third output terminal, wherein the third logic gate circuit is connected to the first voltage domain and the inverter circuit is connected to the second voltage domain. ### Claim 7 (depends on 6) The circuit of claim 6, wherein: the first logic gate circuit comprises a first NAND gate comprising a first plurality of input terminals connected to a corresponding plurality of input signal lines, the first plurality of input terminals including the first input terminal; and the second logic gate circuit comprises a second NAND gate comprising: a second plurality of input terminals connected to the corresponding plurality of input signal lines, the second plurality of input terminals including the second input terminal; and a bypass input terminal connected to a bypass signal line. ### Claim 8 (depends on 1) The circuit of claim 1, wherein: the first logic gate circuit comprise a NAND gate connected to a plurality of input signal lines; and the second logic gate circuit comprises a plurality of inverters connected to the plurality of input signal lines and a NOR gate connected to the plurality of inverters. ### Claim 9 (depends on 1) The circuit of claim 1, the second logic gate circuit further comprises a bypass input terminal to set the header control signal line to a voltage that controls the first header transistor to decouple the output voltage rail from the first logic gate circuit. ### Claim 10 (depends on 1) The circuit of claim 1, further comprising: a third logic gate circuit to implement the first type of Boolean function and comprising a third input terminal connected to the input signal line and a third output terminal connected to a second output signal line; a fourth logic gate circuit to implement the second type of Boolean function and comprising the second input terminal connected to the input signal line and a fourth output terminal connected to a second header control signal line; a third header transistor to switchably couple the output voltage rail to the third logic gate circuit via a third header gate connected to the second header control signal line; and a fourth header transistor to switchably couple the output voltage rail to the fourth logic gate circuit via a fourth header gate connected to the second output signal line. ### Claim 11 A method, comprising: receiving a first input signal in a first voltage domain at a first logic gate circuit, the first logic gate circuit comprising: a first logic function circuit coupled to the first input signal and further coupled between a first output terminal and a reference voltage; and a second logic function circuit coupled to the first input signal and further complementary to the first logic function circuit and coupled between the first output terminal and a first header transistor; operating the first logic gate circuit to perform a first type of Boolean function on the first input signal to generate an output signal in a second voltage domain; receiving the first input signal at a second logic gate circuit, the second logic gate circuit comprising: a third logic function circuit coupled to the first input signal and further coupled between a second output terminal and the reference voltage, the third logic function circuit identical to the first logic function circuit; and a fourth logic function circuit coupled to the first input signal and further complementary to the third logic function circuit and coupled between the second output terminal and a second voltage rail, the fourth logic function circuit identical to the second logic function circuit; operating the second logic gate circuit to perform a second type of Boolean function on the first input signal to generate a header control signal, wherein the second type of Boolean function is a complementary type to the first type of Boolean function; receiving the output signal at a first header gate of the first header transistor to control power supplied to the second logic gate circuit; and receiving the header control signal at a second header gate of a second header transistor to control power supplied to the first logic gate circuit. ### Claim 12 (depends on 11) The method of claim 11, further comprising: receiving a bypass signal at the second logic gate circuit; and based on the bypass signal, setting the header control signal to a steady state to fix the first header transistor in a conducting state. ### Claim 13 (depends on 12) The method of claim 12, further comprising: operating the second logic gate circuit to perform the second type of Boolean function on the first input signal and the bypass signal to output the header control signal in the steady state. ### Claim 14 (depends on 12) The method of claim 12, further comprising: receiving the bypass signal at a bypass transistor to decouple the second logic gate circuit from a power rail to set the header control signal to the steady state. ### Claim 15 (depends on 14) The method of claim 14, further comprising: receiving the bypass signal at a second bypass transistor to couple the second logic gate circuit to a low voltage rail to set the header control signal to the steady state. ### Claim 16 (depends on 11) The method of claim 11, further comprising: operating the first logic gate circuit in the second voltage domain; operating a first portion of the second logic gate circuit in the first voltage domain; and operating a second portion of the second logic gate circuit in the second voltage domain. ### Claim 17 (depends on 16) The method of claim 16, further comprising: operating the first portion of the second logic gate circuit to perform the first type of type of Boolean function on the first input signal; and operating the second portion of the second logic gate circuit to invert an output signal of the first portion of the second logic gate circuit to generate the header control signal in the second voltage domain. ### Claim 18 (depends on 11) The method of claim 11, further comprising: receiving the first input signal at a first input transistor in series with the first header transistor; and receiving a second input signal in the first voltage domain at a second input transistor in parallel with the first header transistor. ### Claim 19 (depends on 11) The method of claim 11, further comprising: receiving the first input signal at a third logic gate circuit comprising a second signal output terminal; and receiving the first input signal at a fourth logic gate circuit comprising a second header control signal output; wherein receiving the first input signal at the fourth logic gate circuit comprises receiving the first input signal at a shared input terminal connected to the second and fourth logic gate circuits. ### Claim 20 A non-transitory computer-readable medium storing computer-readable code for fabrication of an apparatus comprising: a first logic gate circuit to implement a first type of Boolean function and comprising a first input terminal connected to an input signal line and a first output terminal connected to an output signal line, wherein the input signal line is in a first voltage domain and the output signal line is in a second voltage domain, the first logic gate circuit comprising: a first logic function circuit coupled to the input signal line and further coupled between the first output terminal and a reference voltage; and a second logic function circuit coupled to the input signal line and further complementary to the first logic function circuit and coupled between the first output terminal and a first header transistor; a second logic gate circuit to implement a second type of Boolean function and comprising a second input terminal connected to the input signal line and a second output terminal connected to a header control signal line, wherein the second type of Boolean function is a complementary type to the first type of Boolean function, the second logic gate circuit comprising: a third logic function circuit coupled to the input signal line and further coupled between the second output terminal and the reference voltage, the third logic function circuit identical to the first logic function circuit; and a fourth logic function circuit coupled to the input signal line and further complementary to the third logic function circuit and coupled between the second output terminal and a second voltage rail, the fourth logic function circuit identical to the second logic function circuit; the first header transistor to switchably couple an output voltage rail to the first logic gate circuit via a first header gate connected to the header control signal line, wherein the output voltage rail is in the second voltage domain; and a second header transistor to switchably couple the output voltage rail to the second logic gate circuit via a second header gate connected to the output signal line.