# US 12,763,765 B2 · Circuit, system and method related to a dual gate transistor arrangement

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- Number: US 12,763,765 B2
- Document ID: US12763765B2
- Status: Granted
- Kind: B2
- Application number: 19/064,163
- Filed: 2025-02-26
- Published: 2025-09-18
- Granted: 2026-10-13
- Earliest claimed: 2024-03-14
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Daniel Domes; Richard Kuchcinski
- Web page: https://patentgrep.com/patent/US12763765B2

## CPC

- H03K 17/0822: {in field-effect transistor switches}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A circuit includes an input node configured to receive a gate control signal for controlling a dual gate transistor arrangement, a first output node configured to be coupled to a first gate node of the dual gate transistor arrangement, a first switch coupled between the input node and the first output node, and a second output node configured to be coupled to a second gate node of the dual gate transistor arrangement and coupled to the input node. A control circuit is configured to, upon detecting that the gate control signal indicates a turn-off of the dual gate transistor arrangement, open the first switch for a first predefined time period, and close the first switch after the first predefined time period.

## Claims

### Claim 1

A circuit, comprising:
an input node configured to receive a gate control signal for controlling a dual gate transistor arrangement;
a first output node configured to be coupled to a first gate node of the dual gate transistor arrangement;
a first switch coupled between the input node and the first output node;
a second output node configured to be coupled to a second gate node of the dual gate transistor arrangement, and coupled to the input node;
a control circuit configured to:
upon detecting that the gate control signal indicates a turn-off of the dual gate transistor arrangement, open the first switch for a first predefined time period; and
close the first switch after the first predefined time period.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the first switch is a normally-on switch.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the first switch, when open, blocks current from the first output node to the input node.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the first switch is a bidirectional switch.

### Claim 5 (depends on 1)

The circuit of claim 1, further comprising:
a second switch coupled between the input node and the second output node.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the control circuit is configured to:
when closing the first switch after opening the first switch upon detecting that the gate control signal indicates a turn-off of the transistor arrangement, open the second switch for a second predefined time period; and
close the second switch after the second predefined time period.

### Claim 7 (depends on 5)

The circuit of claim 5, wherein the second switch is a normally on switch.

### Claim 8 (depends on 5)

The circuit of claim 5, wherein the second switch, when open, blocks current from the input node to the second output node.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein the second switch is a bidirectional switch.

### Claim 10 (depends on 1)

The circuit of claim 1, further comprising:
a further node configured to be connected to an emitter node of the dual gate transistor arrangement;
at least one third switch coupling the first output node and second output node to the further node,
wherein the control circuit is configured to close the at least one third switch in response to detecting an error event.

### Claim 11 (depends on 10)

The circuit of claim 10, further comprising:
a first diode coupled between the first output node and the at least one third switch; and
a second diode coupled between the second output node and the at least one third switch.

### Claim 12 (depends on 10)

The circuit of claim 10, further comprising:
a second switch coupled between the input node and the second output node,
wherein the control circuit is configured to open the first switch and the second switch in response to detecting the error event.

### Claim 13 (depends on 1)

A device, comprising:
the circuit of claim 1; and
the dual gate transistor arrangement comprising the first gate node and the second gate node,
wherein the first gate node is coupled to the first output node of the circuit and the second gate node is coupled to the second output node of the circuit.

### Claim 14 (depends on 13)

The device of claim 13, further comprising:
a gate terminal coupled to the input node of the circuit;
a collector terminal; and
an emitter terminal,
wherein the dual gate transistor arrangement comprises a collector node coupled to the collector terminal and an emitter node coupled to the emitter terminal.

### Claim 15 (depends on 13)

The device of claim 13, wherein the dual gate transistor arrangement comprises a monolithic dual gate insulated gate bipolar transistor having the first gate node and the second gate node.

### Claim 16 (depends on 13)

The device of claim 13, wherein the dual gate transistor arrangement comprises a first insulated gate bipolar transistor having the first gate node and a second insulated gate bipolar transistor having the second gate node.

### Claim 17 (depends on 16)

The device of claim 16, wherein an emitter of the first insulated gate bipolar transistor is coupled to an emitter of the second insulated gate bipolar transistor, and wherein a collector of the first insulated gate bipolar transistor is coupled to a collector of the second insulated gate bipolar transistor.

### Claim 18

A method, comprising:
receiving a gate control signal indicating a turn-off of a dual gate transistor arrangement;
decoupling a first gate node of the dual gate transistor arrangement from the gate control signal for a first predefined time period; and
coupling the first gate node to the gate control signal after the first predefined time period has elapsed.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
after the first predefined time period has elapsed, decoupling a second gate node of the dual gate transistor arrangement from the gate control signal for a second predetermined time period.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
detecting an error condition; and
in response to detecting the error condition, decoupling both the first gate node and the second gate node from the gate control signal and coupling both the first gate node and the second gate node to an emitter node of the dual gate transistor arrangement.