Duty cycle correction device and duty cycle correction method thereof
AssigneeNanya Technology Corporation
InventorChia-Hao Chang
Life of this patent
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Abstract
A duty cycle correction device and a duty cycle correction method thereof are disclosed. A duty cycle adjustment circuit adjusts a duty cycle of an input clock signal to output an output clock signal. An integrator circuit generates an integral signal according to the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal.
Claims10
A duty cycle correction device, comprising:
- a duty cycle adjustment circuit, adjusting a duty cycle of an input clock signal to output an output clock signal;
- an integrator circuit, coupled to the duty cycle adjustment circuit, generating an integral signal according to the output clock signal;
- and
- a correction control circuit, coupled to the integrator circuit and the duty cycle adjustment circuit, periodically controlling the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal,
- wherein when the logic level of the integral signal changes more than n times during a preset cycle period, the correction control circuit controls the duty cycle adjustment circuit to reduce the adjustment amount.
A duty cycle correction method of a duty cycle correction device, the duty cycle correction device comprising a duty cycle adjustment circuit, wherein the duty cycle adjustment circuit adjusts a duty cycle of an input clock signal to output an output clock signal, and the duty cycle correction method of the duty cycle correction device comprises:
- providing the output clock signal to an integrator circuit to generate an integral signal;
- and
- periodically controlling the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal,
- determining whether the logic level of the integral signal changes more than n times during a preset cycle period;
- and
- when the logic level of the integral signal changes more than n times during the preset cycle period, controlling the duty cycle adjustment circuit to reduce the adjustment amount.
Dependencies are inferred from the claim text.