Ramp-based droop recovery apparatus and method

An integrated circuit (IC) chip comprising:

• a voltage supply circuit to provide a supply voltage;
• a droop recovery circuit responsive to a droop event acting upon the supply voltage, the droop recovery circuit to restore a clock signal from a droop-reduced frequency to a nominal operating frequency, the droop recovery circuit comprising
• a ramp controller to increase the droop reduced frequency to the nominal operating frequency over a sloped-step frequency profile during a recovery timing interval, the sloped-step frequency profile comprising a first ramping from the droop-reduced frequency to a first intermediate frequency that is less than the nominal operating frequency, the sloped-step frequency profile comprising a conditional ramping from the first intermediate frequency to a second intermediate frequency, the conditional ramping based on a detected diminishing of the droop event, wherein the first ramping is in accordance with a first user-programmed ramp rate;
• and
• wherein the conditional ramping is in accordance with a second user-programmed ramp rate that is different than the first user-programmed ramp rate.

A voltage droop recovery circuit, comprising:

• a droop recovery circuit responsive to a droop event acting upon a supply voltage, the droop recovery circuit to restore a clock signal from a droop-reduced frequency to a nominal operating frequency, the droop recovery circuit comprising
• a ramp controller to increase the droop-reduced frequency to the nominal operating frequency over a sloped-step frequency profile during a recovery timing interval, the sloped-step frequency profile comprising ping from the droop-reduced frequency to a first intermediate frequency that is less than the nominal operating frequency, wherein the first intermediate frequency is user-programmable via a first frequency setting and is maintained at a constant value for a first predetermined duration, the first predetermined duration being user-programmable via a first duration setting, the recovery timing interval corresponding to a timing interval representing a diminishing of the droop event;
• and
• a digitally-controlled oscillator (DCO) circuit to generate the clock signal, the DCO responsive to application of a first digital code to generate the droop-reduced frequency, and responsive to iterative application of a progressively increasing digital code to generate the sloped-step frequency profile.

A method of operation in an integrated circuit (IC) chip, the method comprising:

• providing a supply voltage with a voltage supply circuit;
• responding to a droop event acting upon a supply voltage with a droop recovery circuit, the responding including restoring a clock signal from a droop-reduced frequency to a nominal operating frequency, wherein the restoring comprises
• increasing, with a ramp controller, the clock frequency from the droop-reduced frequency to the nominal operating frequency over a sloped-step frequency profile during a recovery timing interval, the sloped-step frequency profile comprising a first ramping from the droop-reduced frequency to a first intermediate frequency that is less than the nominal operating frequency wherein the first intermediate frequency is user-programmable via a first frequency setting and is maintained at a constant value for a first predetermined duration, the first predetermined duration being user programmable via a first duration setting, the recovery timing interval corresponding to a timing interval representing a diminishing of the droop event;
• generating the clock signal with a digitally-controlled oscillator (DCO) circuit;
• responding to application of a first digital code with the DCO to generate the droop-reduced frequency;
• and
• responding to iterative application of a progressively increasing digital code to generate the sloped-step frequency profile.