# US 12,763,756 B2 · Digital filter circuit having plural FIR filter circuits based on predefined filter parallelisms > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,756 B2 - Document ID: US12763756B2 - Status: Granted - Kind: B2 - Application number: 17/540,729 - Filed: 2021-12-02 - Published: 2023-06-08 - Granted: 2026-10-13 - Earliest claimed: 2021-12-02 - Assignees: Rohde & Schwarz GmbH & Co. KG - Applicants: Rohde & Schwarz GmbH & Co. KG - Inventors: Michael Vonbun; Michael Reinhold; Bernhard Nitsch; Adrian Ispas - Web page: https://patentgrep.com/patent/US12763756B2 ## CPC - H03H 17/06: Non-recursive filters - G01R 31/31922: {Timing generation or clock distribution (G01R31/3191 takes precedence)} - H03H 17/0294: {Variable filters; Programmable filters} - H03H 21/0012: {Digital adaptive filters} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A digital filter circuit is described. The digital filter circuit includes a digital filter input, at least two finite impulse response (FIR) filter circuits, and a connection circuit. The digital filter input is configured to receive a digital input signal set having a data parallelism. The at least two FIR filter circuits are configured to process the digital input signal set at least partially. The at least two FIR filter circuits include a pre-adder sub-circuit, a convolution sub-circuit, and a post-adder sub-circuit, respectively. The connection circuit is configured to selectively connect the at least two FIR filter circuits based on the data parallelism of the digital input signal set. ## Claims ### Claim 1 A digital filter circuit, comprising: a digital filter input configured to receive a digital input signal set having a data parallelism; at least two finite impulse response (FIR) filter circuits configured to process the digital input signal set at least partially; and a connection circuit configured to selectively connect the at least two FIR filter circuits based on the data parallelism of the digital input signal set, wherein the at least two FIR filter circuits comprise a pre-adder sub-circuit, a convolution sub-circuit, and a post-adder sub-circuit, respectively, wherein the at least two FIR filter circuits have a predefined filter parallelism, respectively, wherein the connection circuit is configured to selectively connect the at least two FIR filter circuits based on the predefined filter parallelisms of the at least two FIR filter circuits, wherein the connection circuit is configured to connect the at least two FIR filter circuits if the data parallelism of the digital input signal set is bigger than the predefined filter parallelism of at least two FIR filter circuits, and wherein the connection circuit is configured to disconnect the at least two FIR filter circuits from each other if the data parallelism of the digital input signal set is smaller than or equal to the predefined filter parallelism of the at least two FIR filter circuits, wherein a combined structure of the pre-adder sub-circuit, of the convolution sub-circuit, and of the post-adder sub-circuit resembles a matrix decomposition or a transposed matrix decomposition, wherein the connection circuit is configured to selectively connect the post-adder sub-circuits of the at least two FIR filter circuits if said combined structure of the pre-adder sub-circuit, of the convolution sub-circuit, and of the post-adder sub-circuit resembles the matrix decomposition, and wherein the connection circuit is configured to selectively connect the pre-adder sub-circuits of the at least two FIR filter circuits if said combined structure of the pre-adder sub-circuit, of the convolution sub-circuit, and of the post-adder sub-circuit resembles the transposed matrix decomposition. ### Claim 2 (depends on 1) The digital filter circuit of claim 1, wherein the connection circuit comprises at least one multiplexer sub-circuit. ### Claim 3 (depends on 1) The digital filter circuit of claim 1, wherein there are at least two digital input signal sets with different data parallelism, wherein the data parallelism of at least one digital input signal set of the at least two digital input signal sets is greater than the predefined filter parallelism or smaller than the predefined filter parallelism. ### Claim 4 (depends on 3) The digital filter circuit of claim 3, wherein at least one of the at least two FIR filter circuits is configured to process the digital input signal set in a time multiplexing mode if the respective predefined filter parallelism is bigger than the data parallelism of the at least one digital input signal set, and/or wherein the at least two FIR filter circuits are configured to jointly process the digital input signal set if the respective predefined filter parallelism is smaller than the data parallelism of the at least one digital input signal set. ### Claim 5 (depends on 1) The digital filter circuit of claim 1, wherein the at least two FIR filter circuits comprise a short-length FIR filter, respectively. ### Claim 6 (depends on 1) The digital filter circuit of claim 1, wherein the matrix decomposition corresponds to a Coppersmith-Winograd decomposition. ### Claim 7 (depends on 1) The digital filter circuit of claim 1, wherein the at least two FIR filter circuits are arranged in parallel. ### Claim 8 (depends on 1) The digital filter circuit of claim 1, wherein the pre-adder sub-circuit is free of multiplier circuits. ### Claim 9 (depends on 1) The digital filter circuit of claim 1, wherein the post-adder sub-circuit is free of multiplier circuits. ### Claim 10 (depends on 1) The digital filter circuit of claim 1, wherein a parallelism of the digital filter circuit is adjustable. ### Claim 11 (depends on 10) The digital filter circuit of claim 10, wherein the parallelism of the digital filter circuit is adjustable on the fly. ### Claim 12 (depends on 10) The digital filter circuit of claim 10, wherein the parallelism of the digital filter circuit is greater than or equal to 8, and/or wherein the parallelism of the digital filter circuit is smaller than or equal to 256. ### Claim 13 (depends on 1) The digital filter circuit of claim 1, wherein the at least two FIR filter circuits are configured for block-wise processing of samples. ### Claim 14 (depends on 1) The digital filter circuit of claim 1, wherein the digital filter circuit comprises a sample history memory, wherein the sample history memory is configured to accumulate a predefined number of samples. ### Claim 15 (depends on 14) The digital filter circuit of claim 14, wherein the sample history memory is configured to selectively forward the accumulated samples to the at least two FIR filter circuits. ### Claim 16 (depends on 1) The digital filter circuit of claim 1, wherein the digital filter circuit comprises at least two delay sub-circuits. ### Claim 17 A digital filter circuit, comprising: a digital filter input configured to receive a digital input signal set having a data parallelism; at least two finite impulse response (FIR) filter circuits configured to process the digital input signal set at least partially; and a connection circuit configured to selectively connect the at least two FIR filter circuits based on the data parallelism of the digital input signal set, wherein the at least two FIR filter circuits comprise a pre-adder sub-circuit, a convolution sub-circuit, and a post-adder sub-circuit, respectively, wherein the at least two FIR filter circuits have a predefined filter parallelism, respectively, wherein the connection circuit is configured to selectively connect the at least two FIR filter circuits based on the predefined filter parallelisms of the at least two FIR filter circuits, wherein the connection circuit is configured to connect the at least two FIR filter circuits if the data parallelism of the digital input signal set is bigger than the predefined filter parallelism of at least two FIR filter circuits, and wherein the connection circuit is configured to disconnect the at least two FIR filter circuits from each other if the data parallelism of the digital input signal set is smaller than or equal to the predefined filter parallelism of the at least two FIR filter circuits, and wherein the parallelism of the digital filter circuit is adjustable on the fly, wherein the parallelism of the digital filter circuit is adjustable during operation of the digital filter circuit.