# US 12,763,740 B2 · Power amplifier circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,740 B2 - Document ID: US12763740B2 - Status: Granted - Kind: B2 - Application number: 18/392,166 - Filed: 2023-12-21 - Published: 2024-04-18 - Granted: 2026-10-13 - Earliest claimed: 2021-06-24 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Yoshiaki Sukemori; Kenji Tahara - Web page: https://patentgrep.com/patent/US12763740B2 ## CPC - H03F 3/245: {with semiconductor devices only} - H01P 5/16: Conjugate devices, i.e. devices having at least one port decoupled from one other port - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier - H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F: AMPLIFIERS - H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B) ## Abstract There is provided a power amplifier circuit capable of adjusting the gain according to the power mode. A power amplifier circuit includes: a splitter outputting an input signal by splitting the input signal to a signal RF1 and a signal RF2; amplifiers connected to the splitter; and an amplifier provided in or on a signal path branching from between the splitter and an input of the amplifier, connected in parallel with the amplifier, and connected to a biasing terminal supplied with a third bias current or voltage. ## Claims ### Claim 1 A power amplifier circuit comprising: an input signal path to which an input signal is input; a splitter connected to the input signal path, and configured to split the input signal into a first signal and a second signal and to output the first signal and the second signal; a first signal path connected to the splitter and through which the first signal travels; a second signal path connected to the splitter and through which the second signal travels; a first amplifier in the first signal path and connected to a first biasing terminal, the first amplifier being supplied with a first bias current or a first bias voltage from the first biasing terminal; a second amplifier in the second signal path and connected to a second biasing terminal, the second amplifier being supplied with a second bias current or a second bias voltage from the second biasing terminal; a third signal path branching from a node between the splitter and an input of the first amplifier; a third amplifier in the third signal path, connected in parallel with the first amplifier, and connected to a third biasing terminal, the third amplifier being supplied with a third bias current or a third bias voltage from the third biasing terminal; at least one impedance circuit element connected to the third amplifier; a first amplifier section in the first signal path, connected to an output of the first amplifier and to an output of the third amplifier, and configured to output a third signal based on the first signal; a second amplifier section in the second signal path, connected to an output of the second amplifier, and configured to output a fourth signal based on the second signal; and a combiner connected to the first signal path and to the second signal path, and configured to combine the third signal and the fourth signal and to output a fifth signal. ### Claim 2 (depends on 1) The power amplifier circuit according to claim 1, further comprising: a first biasing circuit configured to supply the first bias current or the first bias voltage through the first biasing terminal; a second biasing circuit configured to supply the second bias current or the second bias voltage through the second biasing terminal; a third biasing circuit configured to supply the third bias current or the third bias voltage through the third biasing terminal; and a control circuit configured to control the first biasing circuit, the second biasing circuit, and the third biasing circuit, wherein the control circuit is configured to: control the first biasing circuit, the second biasing circuit, and the third biasing circuit in a first power mode such that the first bias current or the first bias voltage is supplied to the first amplifier, the second bias current or the second bias voltage is supplied to the second amplifier, and the third bias current or the third bias voltage is not supplied to the third amplifier, and control the first biasing circuit, the second biasing circuit, and the third biasing circuit in a second power mode in which a power level is lower than in the first power mode such that the first bias current or the first voltage is not supplied to the first amplifier, the second bias current or the second bias voltage is not supplied to the second amplifier, and the third bias current or the third bias voltage is supplied to the third amplifier. ### Claim 3 (depends on 2) The power amplifier circuit according to claim 2, wherein in a third power mode in which the power level is lower than in the first power mode and higher than in the second power mode, the control circuit is configured to control the first biasing circuit, the second biasing circuit, and the third biasing circuit such that the first bias current or the first bias voltage is supplied to the first amplifier, the second bias current or the second bias voltage is not supplied to the second amplifier, and the third bias current or the third bias voltage is not supplied to the third amplifier. ### Claim 4 (depends on 1) The power amplifier circuit according to claim 1, wherein the first amplifier is a first transistor; wherein the third amplifier is a second transistor; and wherein an emitter size of the second transistor is smaller than an emitter size of the first transistor. ### Claim 5 (depends on 1) The power amplifier circuit according to claim 1, wherein at least one of the impedance circuit elements has a first end connected to the input of the first amplifier and a second end connected to an input of the third amplifier. ### Claim 6 (depends on 1) The power amplifier circuit according to claim 1, wherein at least one of the impedance circuit elements is connected between the third amplifier and ground. ### Claim 7 (depends on 1) The power amplifier circuit according to claim 1, wherein at least one of the impedance circuit elements is connected between the third amplifier and a power supply configured to supply power to the third amplifier. ### Claim 8 (depends on 1) The power amplifier circuit according to claim 1, comprising at least two impedance circuit elements, wherein at least one of the impedance circuit elements has a first end connected to the first biasing terminal and a second end connected to the third biasing terminal. ### Claim 9 A power amplifier circuit comprising: a fourth signal path to which an input signal is input through an input end; a fourth amplifier in the fourth signal path and connected to a fourth biasing terminal, the fourth amplifier being supplied with a fourth bias current or a fourth bias voltage from the fourth biasing terminal; a fifth signal path branching from a node between the input end and an input of the fourth amplifier; a fifth amplifier in the fifth signal path, connected in parallel with the fourth amplifier, and connected to a fifth biasing terminal, the fifth amplifier being supplied with a fifth bias current or a fifth bias voltage from the fifth biasing terminal; at least one impedance circuit element in the fifth signal path, having a first end connected to the input of the fourth amplifier, and a second end connected to an input of the fifth amplifier; a splitter connected to an output of the fourth amplifier and to an output of the fifth amplifier, and configured to split the input signal into a seventh signal and an eighth signal and to output the seventh signal and the eighth signal; a sixth signal path connected to the splitter and through which the seventh signal travels; a seventh signal path connected to the splitter and through which the eighth signal travels; a third amplifier section in the sixth signal path and configured to output a ninth signal based on the seventh signal; a fourth amplifier section in the seventh signal path and configured to output a tenth signal based on the eighth signal; and a combiner connected to an output of the third amplifier section and to an output of the fourth amplifier section, and configured to combine the ninth signal and the tenth signal and to output an eleventh signal. ### Claim 10 (depends on 9) The power amplifier circuit according to claim 9, further comprising: a fourth biasing circuit configured to supply the fourth bias current or the fourth bias voltage through the fourth biasing terminal; a fifth biasing circuit configured to supply the fifth bias current or the fifth bias voltage through the fifth biasing terminal; and a control circuit configured to control the fourth biasing circuit and the fifth biasing circuit, wherein the control circuit is configured to: control the fourth biasing circuit and the fifth biasing circuit in a fourth power mode such that the fourth bias current or the fourth bias voltage is supplied to the fourth amplifier, and the fifth bias current or the fifth bias voltage is not supplied to the fifth amplifier, and control the fourth biasing circuit and the fifth biasing circuit in a fifth power mode in which a power level is lower than in the fourth power mode such that the fourth bias current or the fourth bias voltage is not supplied to the fourth amplifier, and the fifth bias current or the fifth bias voltage is supplied to the fifth amplifier. ### Claim 11 (depends on 10) The power amplifier circuit according to claim 10, further comprising: a sixth biasing circuit configured to supply a sixth bias current or a sixth bias voltage to the third amplifier section; and a seventh biasing circuit configured to supply a seventh bias current or a seventh bias voltage to the fourth amplifier section, wherein the control circuit is further configured to control the sixth biasing circuit and the seventh biasing circuit, and wherein in a sixth power mode in which the power level is lower than in the fourth power mode and higher than in the fifth power mode, the control circuit is configured to control the fourth biasing circuit and the fifth biasing circuit such that the fourth bias current or the fourth bias voltage is not supplied to the fourth amplifier, the fifth bias current or the fifth bias voltage is supplied to the fifth amplifier, the sixth bias current or the sixth bias voltage is not supplied to the third amplifier, and the seventh bias current or the seventh bias voltage is not supplied to the fourth amplifier. ### Claim 12 (depends on 9) The power amplifier circuit according to claim 9, wherein the fourth amplifier is a third transistor; wherein the fifth amplifier is a fourth transistor; and wherein an emitter size of the fourth transistor is smaller than an emitter size of the third transistor. ### Claim 13 (depends on 9) The power amplifier circuit according to claim 9, wherein at least one of the impedance circuit elements has a first end connected to the input of the fourth amplifier and a second end connected to the input of the fifth amplifier. ### Claim 14 (depends on 9) The power amplifier circuit according to claim 9, wherein at least one of the impedance circuit elements is connected between the fifth amplifier and ground. ### Claim 15 (depends on 9) The power amplifier circuit according to claim 9, wherein at least one of the impedance circuit elements is connected between the fifth amplifier and a power supply configured to supply power to the fifth amplifier. ### Claim 16 (depends on 9) The power amplifier circuit according to claim 9, comprising at least two impedance circuit elements, wherein at least one of the impedance circuit elements has a first end connected to the fourth biasing terminal and a second end connected to the fifth biasing terminal. ### Claim 17 A power amplifier circuit comprising: an input signal path to which an input signal is input; a splitter connected to the input signal path, and configured to split the input signal to a first signal and a second signal and to output the first signal and the second signal; a first signal path connected to the splitter and through which the first signal travels; a second signal path connected to the splitter and through which the second signal travels; a first amplifier in the first signal path and connected to a first biasing terminal, the first amplifier being supplied with a first bias current or a first bias voltage from the first biasing terminal; a second amplifier in the second signal path and connected to a second biasing terminal, the second amplifier being supplied with a second bias current or a second bias voltage from the second biasing terminal; a third signal path branching from a node between the splitter and an input of the first amplifier; a third amplifier in the third signal path, connected in parallel with the first amplifier, and connected to a third biasing terminal, the third amplifier being supplied with a third bias current or a third bias voltage from the third biasing terminal; at least one circuit impedance element connected to the third amplifier; and a combiner connected to the first signal path and to the second signal path, and configured to combine a third signal based on the first signal and a fourth signal based on the second signal, and to output a fifth signal. ### Claim 18 (depends on 17) The power amplifier circuit according to claim 17, wherein the first amplifier is a first transistor; wherein the third amplifier is a second transistor; and wherein an emitter size of the second transistor is smaller than an emitter size of the first transistor. ### Claim 19 (depends on 17) The power amplifier circuit according to claim 17, further comprising: a first biasing circuit configured to supply the first bias current or the first bias voltage through the first biasing terminal; a second biasing circuit configured to supply the second bias current or the second bias voltage through the second biasing terminal; a third biasing circuit configured to supply the third bias current or the third bias voltage through the third biasing terminal; and a control circuit configured to control the first biasing circuit, the second biasing circuit, and the third biasing circuit, wherein the control circuit is configured to: control the first biasing circuit, the second biasing circuit, and the third biasing circuit in a first power mode such that the first bias current or the first bias voltage is supplied to the first amplifier, the second bias current or the second bias voltage is supplied to the second amplifier, and the third bias current or the third bias voltage is not supplied to the third amplifier, and control the first biasing circuit, the second biasing circuit, and the third biasing circuit in a second power mode in which a power level is lower than in the first power mode such that the first bias current or the first bias voltage is not supplied to the first amplifier, the second bias current or the second bias voltage is not supplied to the second amplifier, and the third bias current or the third bias voltage is supplied to the third amplifier. ### Claim 20 (depends on 19) The power amplifier circuit according to claim 19, wherein in a third power mode in which the power level is lower than in the first power mode and higher than in the second power mode, the control circuit is configured to control the first biasing circuit, the second biasing circuit, and the third biasing circuit such that the first bias current or the first bias voltage is supplied to the first amplifier, the second bias current or the second bias voltage is not supplied to the second amplifier, and the third bias current or the third bias voltage is not supplied to the third amplifier.