US 12,763,739 B2Granted

Delay-line method for slew rate control for class d driver

AssigneeNuvoton Technology Corporation

InventorsBal Sandhu, Chang-Xian Wu

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Abstract

A class-D amplifier includes: a p-type output transistor; an n-type output transistor connected in series with the p-type output transistor; and a drive circuit connected to a gate of the p-type output transistor and a gate of the n-type output transistor. The drive circuit receives an input signal, generates a p-type output transistor control signal applied to the gate of the p-type output transistor, and generates an n-type output transistor control signal applied to the gate of the n-type output transistor. When the input signal becomes logic high, the n-type output transistor control signal becomes logic low fast, while the p-type output transistor control signal becomes logic low gradually. When the input signal becomes logic low, the p-type output transistor control signal becomes logic high fast, while the n-type output transistor control signal becomes logic high gradually.

Claims20

Dependent claims

A class-D amplifier, comprising:

a p-type output transistor;
an n-type output transistor connected in series with the p-type output transistor;
and
a drive circuit connected to a gate of the p-type output transistor and a gate of the n-type output transistor, wherein the drive circuit receives an input signal, and the drive circuit generates, in response to the input signal, a p-type output transistor control signal applied to the gate of the p-type output transistor, and the drive circuit generates, in response to the input signal, an n-type output transistor control signal applied to the gate of the n-type output transistor;
wherein the drive circuit comprises a multi-bit delay line circuit that receives the input signal and generates a plurality of delayed input signals, and a current digital-to-analog converter configured to generate a current in response to the plurality of delayed input signals, and wherein the drive circuit generates the p-type output transistor control signal and the n-type output transistor control signal based on the current;
wherein when the input signal becomes logic high, the n-type output transistor control signal becomes logic low fast, while the p-type output transistor control signal becomes logic low gradually;
and
wherein when the input signal becomes logic low, the p-type output transistor control signal becomes logic high fast, while the n-type output transistor control signal becomes logic high gradually.

5 more elements

A method for operating a class-D amplifier comprising a p-type output transistor and an n-type output transistor connected in series with the p-type output transistor, the method comprising:

receiving an input signal;
generating, using a drive circuit connected to a gate of the n-type output transistor and a gate of the p-type output transistor, a p-type output transistor control signal in response to the input signal;
generating, using the drive circuit, an n-type output transistor control signal in response to the input signal;
applying the p-type output transistor control signal to the gate of the p-type output transistor;
and
applying the n-type output transistor control signal to the gate of the n-type output transistor;
and
generating, using a multi-bit delay line circuit, a plurality of delayed input signals from the input signal;
generating, using a current digital-to-analog converter, a current in response to the plurality of delayed input signals;
generating the p-type output transistor control signal and the n-type output transistor control signal based on the current;
wherein when the input signal becomes logic high, the n-type output transistor control signal becomes logic low fast, while the p-type output transistor control signal becomes logic low gradually, and wherein when the input signal becomes logic low, the p-type output transistor control signal becomes logic high fast, while the n-type output transistor control signal becomes logic high gradually.

8 more elements

Dependencies are inferred from the claim text.