US 12,763,738 B2Granted

Class-D amplifier

AssigneeRichtek Technology Corporation

InventorYao-Chun Kuo

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Abstract

A class-D amplifier includes a loop filter, a PWM generator coupled to the loop filter, a first multiplexer coupled to the PWM generator, a second multiplexer coupled to the PWM generator, and a power stage coupled to the first multiplexer and the second multiplexer. The loop filter is used to generate positive and negative LPF signals according to first and second analog signals, and first and a second feedback signals. The PWM generator is used to generate positive and negative PWM signals according to the positive and negative LPF signals respectively. The first and second multiplexer are used to output first and second MUX signals selected from a signal group. The power stage is used to generate a positive output signal to a positive output terminal according to the first MUX signal, and a negative output signal to a negative output terminal according to the second MUX signal.

Claims20

Dependent claims

A class-D amplifier comprising:

a loop filter (LPF) configured to generate a positive LPF signal and a negative LPF signal according to a first analog signal, a second analog signal, a first feedback signal and a second feedback signal;
a pulse-width modulation (PWM) generator coupled to the loop filter, configured to generate a first positive PWM signal and a first negative PWM signal according to the positive LPF signal and the negative LPF signal respectively;
a first multiplexer (MUX) coupled to the PWM generator, configured to output a first MUX signal selected from a signal group comprising the first positive PWM signal and/or the first negative PWM signal;
a second multiplexer coupled to the PWM generator, configured to output a second MUX signal selected from the signal group;
and
a power stage coupled to the first multiplexer and the second multiplexer, configured to generate a positive output signal to a positive output terminal according to the first MUX signal, and a negative output signal to a negative output terminal according to the second MUX signal.

3 more elements

An amplifier, comprising:

a master chip comprising,
a loop filter (LPF) configured to generate a positive LPF signal and a negative LPF signal according to a first analog signal, a second analog signal, a first feedback signal and a second feedback signal;
a pulse-width modulation (PWM) generator coupled to the loop filter, configured to generate a positive PWM signal and a negative PWM signal according to the positive LPF signal and the negative LPF signal respectively;
a first multiplexer (MUX) coupled to the PWM generator, configured to output a first MUX signal selected from a signal group comprising the positive PWM signal and the negative PWM signal;
a second multiplexer coupled to the PWM generator, configured to output a second MUX signal selected from the signal group;
and
a power stage coupled to the first multiplexer and the second multiplexer, configured to generate a positive output signal to a positive output terminal according to the first MUX signal, and a negative output signal to a negative output terminal according to the second MUX signal;
and
a slave chip comprising:
a loop filter (LPF);
a pulse-width modulation (PWM) generator coupled to the loop filter;
a first multiplexer (MUX) coupled to the PWM generator of the master chip and the PWM generator of the slave chip, configured to output a first MUX signal selected from the signal group;
a second multiplexer coupled to the PWM generators of the master chip and the slave chip, configured to output a second MUX signal selected from the signal group;
and
a power stage coupled to the first multiplexer and the second multiplexer of the slave chip, configured to generate a positive output signal to a positive output terminal according to the first MUX signal output by the first MUX of the slave chip, and a negative output signal to a negative output terminal according to the second MUX signal output by the second MUX of the slave chip;
wherein the master chip and the slave chip form a parallel bridge-tied load (PBTL) configuration.

13 more elements

Dependencies are inferred from the claim text.