Analog references for high voltage input-output with improved bias current

An apparatus comprising:

• an input-output positive supply voltage rail;
• an input-output negative supply voltage rail;
• a plurality of transistor chains comprising at least:
• a first transistor chain connected to the input-output positive supply voltage rail and to the input-output negative supply voltage rail, wherein at least a first gate of at least a first transistor of the first transistor chain is connected to a first control signal to enable and disable a first current between the input-output positive supply voltage rail and the input-output negative supply voltage rail via the first transistor chain;
• a second transistor chain connected to the input-output positive supply voltage rail and to the input-output negative supply voltage rail, wherein at least a first gate of at least a first transistor of the second transistor chain is connected to a second control signal to enable and disable a second current between the input-output positive supply voltage rail and the input-output negative supply voltage rail via the second transistor chain;
• and
• a reference voltage output rail driven by the first transistor chain and the second transistor chain, wherein a bias current on the reference voltage output rail is based upon a number of transistor chains that are enabled from among the plurality of transistor chains.

A method for generating a reference voltage for an input-output ring of an integrated circuit, comprising:

• applying an output of a first amplifier loop to at least a first gate of at least a first transistor of a first outer ballast stage of the integrated circuit, the first outer ballast stage comprising a first transistor chain connected to an input-output positive supply voltage rail and to an input-output negative supply voltage rail;
• receiving a first control signal associated with a first bias current for a first reference voltage;
• activating, in accordance with the first control signal, the first outer ballast stage of the integrated circuit, wherein at least a second gate of at least a second transistor of the first outer ballast stage is connected to the first control signal to enable and disable the first outer ballast stage, wherein the first bias current for the first reference voltage is dependent upon a number of outer ballast stages that are activated from among a first plurality of outer ballast stages, where the first plurality of outer ballast stages includes the first outer ballast stage, wherein the first reference voltage is generated via at least the first outer ballast stage when activated;
• and
• applying the first reference voltage with the first bias current to an input-output stage of the integrated circuit.