# US 12,763,733 B2 · Cascode amplifier with dynamic body bias and method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,733 B2 - Document ID: US12763733B2 - Status: Granted - Kind: B2 - Application number: 18/400,013 - Filed: 2023-12-29 - Published: 2025-07-03 - Granted: 2026-10-13 - Earliest claimed: 2023-12-29 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corp. - Inventors: Ting-Hsu Chien; Chia-Liang (Leon) Lin - Web page: https://patentgrep.com/patent/US12763733B2 ## CPC - H03F 1/3205: {in field-effect transistor amplifiers} - H03F 3/16: with field-effect devices - H03F: AMPLIFIERS ## Abstract A cascode amplifier comprises: a common-source amplifier includes a first MOST (metal-oxide semiconductor transistor) of a first type configured to receive a first input signal and output a first current to a first node in accordance with a body voltage applied at a body of the first MOST of the first type; a first common-gate amplifier comprising a second MOST of the first type and configured to receive the first current from the first node and output a second current to a second drain node in accordance with a first gate voltage; a dynamic body voltage generator configured to receive the first input signal and output the body voltage; and a load configured to establish a third voltage at a third drain node in response to the second current through a DC (direct current) path between the second drain node and the third drain node. ## Claims ### Claim 1 A cascode amplifier comprises: a common-source amplifier (CSA) comprising a first MOST (metal-oxide semiconductor transistor) of a first type configured to receive a first input signal and output a first current to a first drain node in accordance with a body voltage applied at a body of the first MOST of the first type; a first common-gate amplifier (CGA) comprising a second MOST of the first type and configured to receive the first current from the first drain node and output a second current to a second drain node in accordance with a first gate voltage; a dynamic body voltage generator configured to receive the first input signal and output the body voltage; and a load configured to establish a third drain voltage at a third drain node in response to the second current through a DC (direct current) path between the second drain node and the third drain node, wherein: the dynamic body voltage generator comprises a third MOST of a second type configured to output a dynamic current in accordance with the first input signal, and a first resistor configured to establish the body voltage in response to the dynamic current. ### Claim 2 (depends on 1) The cascode amplifier of claim 1, wherein the load is a resonant network configured to have a high impedance at a frequency of the first input signal. ### Claim 3 (depends on 2) The cascode amplifier of claim 2, wherein the load comprises an inductor configured to provide a DC coupling between the third drain node and a second DC node. ### Claim 4 (depends on 3) The cascode amplifier of claim 3 further comprising a capacitor connected in parallel with the inductor. ### Claim 5 (depends on 1) The cascode amplifier of claim 1, wherein a gate of the third MOST of the second type is coupled to the first input signal through an AC (alternating current) coupling capacitor, and DC coupled to a first bias node through a second resistor. ### Claim 6 (depends on 1) The cascode amplifier of claim 1, wherein the DC path comprises a short circuit inserted between the second drain node and the third drain node. ### Claim 7 (depends on 1) The cascode amplifier of claim 1, wherein the DC path comprises a second CGA comprising a fourth MOST of the first type and configured to relay the second current into a third current directed to the third drain node in accordance with a second gate voltage. ### Claim 8 (depends on 1) The cascode amplifier of claim 1 further comprising a neutralization capacitor configured to couple a second input signal to the first drain node, wherein the second input signal is an inversion of the first input signal. ### Claim 9 (depends on 1) The cascode amplifier of claim 1 further comprising a dynamic gate voltage generator configured to output the first gate voltage in accordance with an AC (alternate current) swing of the first input signal. ### Claim 10 (depends on 9) The cascode amplifier of claim 9, wherein the dynamic gate voltage generator comprises a peak detector configured to detect a peak of the first input signal and output the first gate voltage to represent the peak. ### Claim 11 A method of signal amplification comprising: receiving a first input signal; converting the first input signal into a first current directed to a first drain node using a common-source amplifier (CSA) comprising a first MOST (metal-oxide semiconductor transistor) of a first type, wherein a source, a gate, a drain, and a body of the first MOST of the first type connect to a first DC (direct current) node, the first input signal, the first drain node, and a body voltage, respectively; relaying the first current into a second current directed to a second drain node using a first common-gate amplifier (CGA) comprising a second MOST of the first type, wherein a source, a gate, and a drain of the second MOST of the first type connect to the first drain node, a first gate voltage, and the second drain node, respectively; adjusting the body voltage using a third MOST of a second type configured in a common-source amplifier topology to receive an AC (alternate current) coupling of the first input signal and output the body voltage; and establishing a third drain voltage at a third drain node by directing the second current to the third drain node through a DC (direct current) path and terminating the third drain node with a load comprising an inductor configured to provide DC coupling between the third drain node and a second DC node. ### Claim 12 (depends on 11) The method of signal amplification of claim 11 further comprising coupling a second input signal to the first drain node using a neutralization capacitor, wherein the second input signal is an inversion of the first input signal. ### Claim 13 (depends on 11) The method of signal amplification of claim 11, wherein the DC path comprises a short circuit inserted between the second drain node and the third drain node. ### Claim 14 (depends on 11) The method of signal amplification of claim 11 further comprising relaying the second current into a third current directed to the third drain node using a second CGA comprising a fourth MOST of the first type, wherein a source, a gate, and a drain of the fourth MOST of the first type connect to the second drain node, a second gate voltage, and the third drain node. ### Claim 15 (depends on 11) The method of signal amplification of claim 11, wherein the load is configured to have a high impedance at a frequency of the first input signal. ### Claim 16 (depends on 11) The method of signal amplification of claim 11, wherein the load further comprises a capacitor connected in parallel with the inductor. ### Claim 17 (depends on 11) The method of signal amplification of claim 11 further comprising dynamically adjusting the first gate voltage in accordance with an AC swing of the first input signal. ### Claim 18 (depends on 17) The method of signal amplification of claim 17, wherein dynamically adjusting the first gate voltage comprising using a dynamic gate voltage generator that comprises a peak detector configured to detect a peak of the first input signal and output the first gate voltage to represent the peak. ### Claim 19 (depends on 11) The method of signal amplification of claim 11, wherein a source, a gate, and a drain of the third MOST of the second type connect to a second DC node, a third gate node, and the body of the first MOST of the first type, respectively, the drain is terminated with a first resistor, and the third gate node is AC coupled to the first input signal and DC coupled to a first bias node through a second resistor.