# US 12,763,728 B2 · Data driving circuit and display including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,728 B2 - Document ID: US12763728B2 - Status: Granted - Kind: B2 - Application number: 19/210,637 - Filed: 2025-05-16 - Published: 2025-09-04 - Granted: 2026-10-13 - Earliest claimed: 2022-10-13 - Assignees: Lx Semicon Co., Ltd. - Applicants: Lx Semicon Co., Ltd. - Inventors: Yong Sung Ahn; Ji Won Kim; Hyo Joong Kim; Kyung Min Shin; Kyu Tae Lee; Ha Rim Choi - Web page: https://patentgrep.com/patent/US12763728B2 ## CPC - H03F 1/02: Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation - G09G 3/2007: {Display of intermediate tones} - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3275: Details of drivers for data electrodes - H03F 3/45076: {characterised by the way of implementation of the active amplifying circuit in the differential amplifier} - H03F 3/68: Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2320/0673: for control of gamma adjustment, e.g. selecting another gamma curve - H03F 2203/45044: One or more switches are opened or closed to balance the dif amp to reduce the offset of the dif amp - H03F 2203/45214: Offset in a differential amplifier being reduced by control of the substrate voltage, the voltage being either fixed or variable - H03F 2203/45296: the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor - H03F: AMPLIFIERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract The present disclosure relates to an offset elimination operation of an internal operational amplifier of a data driving circuit and relates to a technique that applies different offset elimination methods for each position of an operational amplifier. ## Claims ### Claim 1 A gamma voltage generation circuit comprising: a resistor string; a first operational amplifier circuit connected to an uppermost end of the resistor string and configured to output a first voltage corresponding to a highest voltage of the resistor string; a second operational amplifier circuit connected to a lowest end of the resistor string and configured to output a second voltage corresponding to a lowest voltage of the resistor string; and a third operational amplifier circuit connected to a node of the resistor string and configured to divide the first voltage and the second voltage and to output a third voltage, wherein the third operational amplifier circuit includes a first offset elimination circuit configured to eliminate an offset voltage through charging and discharging of a capacitor by an Auto-Zeroing method, the Auto-Zeroing method including storing the offset voltage in the capacitor during a sampling interval and eliminating the offset voltage during a different interval based on the stored voltage, and the first operational amplifier circuit and the second operational amplifier circuit are configured to eliminate an offset voltage by a chopping method including periodically switching connections of input and output terminals, and wherein the Auto-Zeroing method is applied to the third operational amplifier circuit connected to the node of the resistor string, and the chopping method is applied to the first operational amplifier circuit and the second operational amplifier circuit connected to opposite ends of the resistor string, such that different offset elimination methods are selectively applied according to positions of the operational amplifier circuits. ### Claim 2 (depends on 1) The gamma voltage generation circuit of claim 1, wherein the first offset elimination circuit is configured to perform a sampling operation in a first time interval to charge an offset voltage of a first sub-operational amplifier circuit to a first capacitor and perform an offset elimination operation in a second time interval to eliminate the offset voltage of the first sub-operational amplifier circuit based on a voltage stored in the first capacitor. ### Claim 3 (depends on 1) The gamma voltage generation circuit of claim 1, wherein the first offset elimination circuit includes: a first sub-operational amplifier; a first switch electrically connected to a first input terminal of the first sub-operational amplifier; a first capacitor electrically connected to a second input terminal of the first sub-operational amplifier and configured to store an offset voltage of the first sub-operational amplifier; a second switch electrically connected to the second input terminal and an output terminal of the first sub-operational amplifier and forming a common node with the first capacitor; a third switch electrically connected to the first switch and the first capacitor and forming a common node with the first switch and the first capacitor; and a fourth switch electrically connected to the output terminal of the first sub-operational amplifier. ### Claim 4 (depends on 3) The gamma voltage generation circuit of claim 3, wherein, in the first offset elimination circuit, the first switch and the second switch are turned on and the third switch and the fourth switch are turned off in a first time interval to store the offset voltage of the first sub-operational amplifier in the first capacitor, and the first switch and the second switch are turned off and the third switch and the fourth switch are turned on in a second time interval to eliminate the offset voltage of the first sub-operational amplifier. ### Claim 5 (depends on 4) The gamma voltage generation circuit of claim 4, wherein the third operational amplifier circuit further includes a second offset elimination circuit configured to eliminate an offset voltage through charging and discharging a capacitor, and the second offset elimination circuit is configured to perform an offset elimination operation in the first time interval to eliminate an offset voltage of a second sub-operational amplifier circuit based on a voltage stored in a second capacitor and perform a sampling operation in the second time interval to charge the offset voltage of the second sub-operational amplifier circuit to the second capacitor. ### Claim 6 (depends on 5) The gamma voltage generation circuit of claim 5, wherein the first offset elimination circuit and the second offset elimination circuit are connected in parallel, and an offset elimination operation of the first offset elimination circuit and an offset elimination operation of the second offset elimination circuit are performed alternately and repeatedly. ### Claim 7 (depends on 6) The gamma voltage generation circuit of claim 6, wherein the second offset elimination circuit has the same circuit structure as the first offset elimination circuit and is configured to share nodes of input/output terminals with the first offset elimination circuit to be connected in parallel. ### Claim 8 (depends on 1) The gamma voltage generation circuit of claim 1, wherein the first operational amplifier circuit and the second operational amplifier circuit include a third offset elimination circuit configured to perform an offset voltage elimination operation by a chopping method including periodically switching connections of input and output terminals, independently of an offset voltage elimination operation of the first offset elimination circuit. ### Claim 9 (depends on 8) The gamma voltage generation circuit of claim 8, wherein the third offset elimination circuit is configured to perform an offset elimination operation by the chopping method including a first chopping switch circuit, a second chopping switch circuit, a third chopping switch circuit and a fourth chopping switch circuit that are turned on and off alternately, the first chopping switch circuit is electrically connected to an input terminal of a third sub-operational amplifier, the second chopping switch circuit is electrically connected to the input terminal of the third sub-operational amplifier, the third chopping switch circuit is electrically connected to an output terminal of the third sub-operational amplifier, the fourth chopping switch circuit is electrically connected to the output terminal of the third sub-operational amplifier, the first chopping switch circuit and the second chopping switch circuit form a common node, and the third chopping switch circuit and the fourth chopping switch circuit form a common node. ### Claim 10 (depends on 9) The gamma voltage generation circuit of claim 9, wherein the first chopping switch circuit and the third chopping switch circuit are configured to be turned on and turned off at the same timing, and the second chopping switch circuit and the fourth chopping switch circuit are configured to be turned on and turned off at the same timing and are configured to perform an operation at a timing opposite to an operation timing of the first chopping switch circuit and the third chopping switch circuit. ### Claim 11 A data driving circuit comprising: a data voltage generation circuit configured to supply a data voltage to a pixel through a data line; and a gamma reference voltage generation circuit configured to distribute a power supply voltage formed at both ends of a resistor string to generate a gamma reference voltage and supply the gamma reference voltage to the pixel through the data line, wherein the gamma reference voltage generation circuit includes: the resistor string; a first operational amplifier circuit connected to a first end of the resistor string; a second operational amplifier circuit connected to a second end of the resistor string; and a third operational amplifier circuit connected to a node of the resistor string, wherein the third operational amplifier circuit includes a first offset elimination circuit configured to eliminate an offset voltage through charging and discharging of a capacitor by an Auto-Zeroing method, the Auto-Zeroing method including storing the offset voltage in the capacitor during a sampling interval and eliminating the offset voltage during a different interval based on the stored voltage, and the first operational amplifier circuit and the second operational amplifier circuit include a third offset elimination circuit configured to eliminate an offset voltage by a chopping method including periodically switching connections of input and output terminals, and wherein the Auto-Zeroing method is applied to the third operational amplifier circuit connected to the node of the resistor string, and the chopping method is applied to the first operational amplifier circuit and the second operational amplifier circuit connected to opposite ends of the resistor string, such that different offset elimination methods are selectively applied according to positions of the operational amplifier circuits. ### Claim 12 (depends on 11) The data driving circuit of claim 11, wherein the third operational amplifier circuit includes the first offset elimination circuit and a second offset elimination circuit connected in parallel, and the second offset elimination circuit is configured to repeatedly perform an offset elimination operation at a sampling operation timing of the first offset elimination circuit and the first offset elimination circuit is configured to perform an offset elimination operation at a sampling operation timing of the second offset elimination circuit. ### Claim 13 (depends on 12) The data driving circuit of claim 12, wherein the first offset elimination circuit and the second offset elimination circuit have the same structure and are configured to be controlled such that turn-on and turn-off timings of internal switches of the first offset elimination circuit and the second offset elimination circuit are opposite to each other. ### Claim 14 (depends on 13) The data driving circuit of claim 13, wherein the first offset elimination circuit includes: a first sub-operational amplifier; a first switch electrically connected to a first input terminal of the first sub-operational amplifier; a first capacitor electrically connected to a second input terminal of the first sub-operational amplifier and configured to store an offset voltage of the first sub-operational amplifier; a second switch electrically connected to the second input terminal and an output terminal of the first sub-operational amplifier and forming a common node with the first capacitor; a third switch electrically connected to the first switch and the first capacitor and forming a common node; and a fourth switch electrically connected to the output terminal of the first sub-operational amplifier. ### Claim 15 (depends on 12) The data driving circuit of claim 12, wherein the first operational amplifier circuit and the second operational amplifier circuit include the third offset elimination circuit that is configured to perform an offset voltage elimination operation independently of offset voltage elimination operations of the first offset elimination circuit and the second offset elimination circuit, and the third offset elimination circuit is configured to perform the offset voltage elimination operation by the chopping method including a first chopping switch circuit, a second chopping switch circuit, a third chopping switch circuit and a fourth chopping switch circuit that are turned on and off alternately. ### Claim 16 (depends on 11) The data driving circuit of claim 11, wherein, in the first operational amplifier circuit, an input terminal is connected to a first multiplexer supplied with a voltage, and an output signal supplied from an output terminal is not divided, and in the second operational amplifier circuit, an input terminal is connected to a second multiplexer supplied with a voltage, and an output signal supplied from an output terminal is not divided. ### Claim 17 A method of eliminating an offset comprising: eliminating an offset voltage of a first operational amplifier circuit connected to a first end of a first resistor string and outputting a first gamma reference voltage; eliminating an offset voltage of a second operational amplifier circuit connected to a second end of the first resistor string and outputting a second gamma reference voltage; eliminating an offset voltage of a third operational amplifier circuit connected to a node of the first resistor string and outputting a third gamma reference voltage; and selecting and supplying a voltage between a maximum reference voltage and a minimum reference voltage through a second resistor string, wherein eliminating the offset voltage of the third operational amplifier circuit includes performing an Auto-Zeroing method including storing the offset voltage in a capacitor during a sampling interval and eliminating the offset voltage during a different interval based on the stored voltage, and eliminating the offset voltage of the first operational amplifier circuit and the second operational amplifier circuit includes performing a chopping method including periodically switching connections of input and output terminals, and wherein the Auto-Zeroing method is performed for the third operational amplifier circuit connected to the node of the first resistor string, and the chopping method is performed for the first and second operational amplifier circuits connected to opposite ends of the first resistor string, such that different offset elimination methods are selectively applied according to positions of the operational amplifier circuits. ### Claim 18 (depends on 17) The method of eliminating an offset of claim 17, wherein the third operational amplifier circuit includes a first offset elimination circuit and a second offset elimination circuit, the first offset elimination circuit performs a sampling operation in a first time interval to charge an offset voltage of a first sub-operational amplifier circuit to a first capacitor and performs an offset elimination operation in a second time interval to eliminate the offset voltage of the first sub-operational amplifier circuit based on a voltage stored in the first capacitor, and the second offset elimination circuit performs an offset elimination operation in the first time interval to eliminate an offset voltage of a second sub-operational amplifier circuit based on a voltage stored in a second capacitor and performs a sampling operation in the second time interval to charge the offset voltage of the second sub-operational amplifier circuit to the second capacitor. ### Claim 19 (depends on 18) The method of eliminating an offset of claim 18, wherein the first offset elimination circuit and the second offset elimination circuit have the same structure, and the first offset elimination circuit includes: a first sub-operational amplifier; a first switch electrically connected to a first input terminal of the first sub-operational amplifier; a first capacitor electrically connected to a second input terminal of the first sub-operational amplifier and storing an offset voltage of the first sub-operational amplifier; a second switch electrically connected to the second input terminal and an output terminal of the first sub-operational amplifier and forming a common node with the first capacitor; a third switch electrically connected to the first switch and the first capacitor and forming a common node; and a fourth switch electrically connected to the output terminal of the first sub-operational amplifier. ### Claim 20 (depends on 19) The method of eliminating an offset of claim 19, wherein a third offset elimination circuit of the first operational amplifier circuit and the second operational amplifier circuit performs an offset elimination operation by the chopping method including a first chopping switch circuit, a second chopping switch circuit, a third chopping switch circuit and a fourth chopping switch circuit that are turned on and off alternately, the first chopping switch circuit is electrically connected to an input terminal of a third sub-operational amplifier, the second chopping switch circuit is electrically connected to the input terminal of the third sub-operational amplifier, the third chopping switch circuit is electrically connected to an output terminal of the third sub-operational amplifier, the fourth chopping switch circuit is electrically connected to the output terminal of the third sub-operational amplifier, the first chopping switch circuit and the second chopping switch circuit form a common node, and the third chopping switch circuit and the fourth chopping switch circuit form a common node.