# US 12,763,162 B2 · Memory device and test method for the memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,162 B2 - Document ID: US12763162B2 - Status: Granted - Kind: B2 - Application number: 18/888,271 - Filed: 2024-09-18 - Published: 2025-07-24 - Granted: 2026-10-13 - Earliest claimed: 2024-01-24 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Byoungjin Ahn; Dongseok Kang; Shinho Kim; Jongwan Kim - Web page: https://patentgrep.com/patent/US12763162B2 ## CPC - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device comprising a memory core including a memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks, a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank, and a control circuit configured to control the parallel test. The BIST circuit may determine at least one defective memory cell outputting a defective bit among target memory cells included in the target memory bank, and may determine whether the defective memory cell is a single defective memory cell or an adjacent double defective memory cell, and the control circuit May determine the target memory bank to be a defective memory bank when the defective memory cell is not the single defective memory cell and the adjacent double defective memory cell. ## Claims ### Claim 1 A memory device comprising: a memory core including a memory cell array including a plurality of memory cells, the memory cell array arranged into a plurality of memory banks; a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank among the plurality of memory banks; and a control circuit configured to control the parallel test, wherein the BIST circuit is configured to determine, in response to a one or more defective memory cells in the target memory bank outputting a defective bit among a plurality of target memory cells in the target memory bank, whether the defective memory cell is a single defective memory cell or an adjacent double defective memory cell, and wherein the control circuit is configured to determine the target memory bank to be a non-defective memory bank when the defective memory cell is the single defective memory cell or the adjacent double defective memory cell. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the BIST circuit is configured to determine an output bit that is in a logical state different from an input bit, among output bits output from the plurality of target memory cells, as the defective bit. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the BIST circuit comprises a first test circuit configured to determine the defective memory cell, a second test circuit configured to determine whether the defective memory cell is the single defective memory cell, and a third test circuit configured to determine whether the defective memory cell is the adjacent double defective memory cell. ### Claim 4 (depends on 3) The memory device of claim 3, wherein when one memory cell among the plurality of target memory cells outputs the defective bit, the second test circuit determines the one memory cell to be the single defective memory cell, and when a pair of memory cells adjacent to each other, among the plurality of target memory cells, output the defective bit, the third test circuit determines the pair of memory cells to be the adjacent double defective memory cell. ### Claim 5 (depends on 4) The memory device of claim 4, wherein each of the plurality of memory banks includes a plurality of word lines and a plurality of bit lines, and the plurality of memory cells are connected to the plurality of word lines and the plurality of bit lines, and the pair of memory cells are connected to one word line among the plurality of word lines and a pair of adjacent bit lines adjacent to each other among the plurality of bit lines. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the pair of bit lines is determined by the control circuit. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the third test circuit includes an input unit, a logic unit including a plurality of half adders, and an output unit for outputting an output signal, wherein the input unit is configured to receive a selection signal for determining the pair of bit lines from the control circuit and bit determination signals indicating whether each of the output bits is a defective bit from the first test circuit, and output the bit determination signals corresponding to the pair of memory cells, among the bit determination signals, to each of the plurality of half adders, the logic unit is configured to output a first internal signal to a third internal signal using the bit determination signals corresponding to the pair of memory cells, and the output unit configured to output an output signal indicating whether the pair of memory cells are the adjacent double defective memory cell using the first internal signal to the third internal signal. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the input unit is configured to output a 2n-1th bit determination signal to an nth half adder and includes a plurality of multiplexers, and an nth multiplexer among the plurality of multiplexers is configured to output one of a 2n-2th bit determination signal and a 2nth bit determination signal to the nth half adder according to the selection signal. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the nth multiplexer is configured to output the 2n-2th bit determination signal to the nth half adder when the selection signal is in a first state, and output the 2nth bit determination signal to the nth half adder when the selection signal is in a second state. ### Claim 10 (depends on 7) The memory device of claim 7, wherein the logic unit includes a first logic unit, a second logic unit, and a third logic unit, wherein the first logic unit includes the plurality of half adders, and each of the plurality of half adders is configured to perform a NAND logic operation and an XNOR logic operation on the bit determination signals corresponding to the pair of memory cells, the second logic unit includes a plurality of second logic circuits, and each of the second logic circuits is configured to perform a first NAND logic operation, a second NAND logic operation, and an XOR logical operation on outputs of a pair of half adders adjacent to each other, among the plurality of half adders, and the third logic unit includes at least one third logic circuit, and the third logic circuit is configured to perform a NAND logic operation, an AND logic operation, and a NOR logic operation on outputs of the second logic unit to output the first internal signal to the third internal signal. ### Claim 11 (depends on 10) The memory device of claim 10, wherein the first internal signal indicates whether, among first to fourth pairs of output bits output from first to fourth pairs of memory cells adjacent to each other among the plurality of target memory cells, the first pair of output bits are defective bits or the second to fourth pairs of output bits are defective bits. ### Claim 12 (depends on 10) The memory device of claim 10, wherein the second internal signal indicates whether among first to fourth pairs of output bits output from first to fourth pairs of memory cells adjacent to each other among the plurality of target memory cells, there are no defective bits, or a pair of output bits are defective bits, among the first and second pairs of output bits, and there are no defective bits, or a pair of output bits are defective bits, among the third and fourth pairs of output bits. ### Claim 13 (depends on 10) The memory device of claim 10, wherein the third internal signal indicates whether each of first to fourth pairs of output bits output from first to fourth pairs of memory cells adjacent to each other among the plurality of target memory cells is identical as a defective bit or a normal bit. ### Claim 14 (depends on 10) The memory device of claim 10, wherein the output unit is configured to output the output signal by performing an AND logical operation on the first internal signal to the third internal signal. ### Claim 15 A memory device comprising: a memory core including a memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks; a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank among the plurality of memory banks; and a control circuit configured to control the parallel test, wherein the BIST circuit includes, for target memory cells included in the target memory bank, a first test circuit configured to determine a defective memory cell and output a first output signal, a second test circuit configured to determine whether the defective memory cell is a single defective memory cell and output a second output signal, and a third test circuit configured to determine whether the defective memory cell is an adjacent double defective memory cell and output a third output signal, and wherein the control circuit is configured to determine the target memory bank to be a non-defective memory bank when the defective memory cell is the single defective memory cell or the adjacent double defective memory cell. ### Claim 16 (depends on 15) The memory device of claim 15, wherein the target memory cells are divided into a plurality of regions, and the BIST circuit is configured to output the first output signal to the third output signal for each of the plurality of regions. ### Claim 17 (depends on 16) The memory device of claim 16, wherein the first test circuit determines at least one memory cell outputting a logic state different from an input bit, among the target memory cells, as the defective memory cell, and outputs the first output signal in a second state with respect to a region including the defective memory cell, among the plurality of regions. ### Claim 18 (depends on 17) The memory device of claim 17, wherein when one memory cell among the target memory cells outputs the logic state different from the input bit, the second test circuit determines the one memory cell to be the single defective memory cell, and outputs the second output signal in a first state with respect to a region including the single defective memory cell among the plurality of regions, and when a pair of memory cells adjacent to each other among the target memory cells output the logic state different from the input bit, the third test circuit determines the pair of memory cells to be the adjacent double defective memory cell, and outputs the third output signal in a first state with respect to a region including the adjacent double defective memory cell among the plurality of regions. ### Claim 19 (depends on 18) The memory device of claim 18, wherein the control circuit determines the target memory bank to be a defective memory bank when the second output signal and the third output signal are not output in the first state, with respect to at least one region among the plurality of regions in which the first output signal is output in a second state. ### Claim 20 A test method for a memory device including a plurality of memory banks, the method comprising: selecting a target memory bank from the plurality of memory banks, and determining a defective memory cell outputting a logic state different from an input bit among target memory cells included in the target memory bank; when the defective memory cell is determined among the target memory cells, determining whether the defective memory cell is a single defective memory cell or an adjacent double defective memory cell; when the defective memory cell is the single defective memory cell or the adjacent double defective memory cell, determining the target memory bank to be a non-defective memory bank.