Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

A memory system comprising:

• a nonvolatile memory (NVM) including a first NVM chip and a second NVM chip;
• and a controller configured to control the NVM,
• wherein the controller comprises:
• a data pin configured to transmit write data through a data bus during a write operation;
• a data strobe pin configured to transmit a data strobe signal through a data strobe signal bus during the write operation, the data strobe signal comprising a preamble section, a toggling section and a postamble section;
• and
• an on-die termination (ODT) pin configured to transmit an ODT signal during the write operation,
• wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, or a read enable signal bus, wherein the termination is enabled during the preamble section of the data strobe signal after the data strobe signal falling, and the termination is disabled during the postamble section of the data strobe signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform an ODT when the write data is written to the second NVM chip and the ODT signal is enabled.

A nonvolatile memory (NVM) device comprising:

• a first NVM chip and a second NVM chip;
• a data pin configured to transmit read data to a controller through a data bus during a read operation;
• a data strobe pin configured to transmit a data strobe signal to the controller through a data strobe signal bus during the read operation;
• a read enable pin configured to receive a read enable signal from the controller through a read enable signal bus during the read operation, the read enable signal comprising a preamble section, a toggling section and a postamble section;
• and
• an on-die termination (ODT) pin configured to receive an ODT signal from the controller during the read operation,
• wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, or the read enable signal bus, wherein the termination is enabled during the preamble section of the read enable signal after the read enable signal falling, and the termination is disabled during the postamble section of the read enable signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform an ODT when the read data is read from the second NVM chip and the ODT signal is enabled.

A nonvolatile memory (NVM) device comprising:

• a first NVM chip and a second NVM chip;
• a data pin configured to receive write data from a controller through a data bus during a write operation;
• a data strobe pin configured to receive a data strobe signal from the controller through a data strobe signal bus during the write operation, the data strobe signal comprising a preamble section, a toggling section and a postamble section;
• and
• an on-die termination (ODT) pin configured to receive an ODT signal from the controller during the write operation,
• wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, or a read enable signal bus, wherein the termination is enabled during the preamble section of the data strobe signal after the data strobe signal falling, and the termination is disabled during the postamble section of the data strobe signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform an ODT when the write data is written to the second NVM chip and the ODT signal is enabled.