# US 12,763,157 B2 · Memory programming schemes with adjustable verification voltages for reducing data retention loss > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,157 B2 - Document ID: US12763157B2 - Status: Granted - Kind: B2 - Application number: 18/775,017 - Filed: 2024-07-17 - Published: 2026-01-22 - Granted: 2026-10-13 - Earliest claimed: 2024-07-17 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Alon Eyal; Alexander Bunin; Michael Tsohar; Nir Tishbi; Asaf Rotenberg - Web page: https://patentgrep.com/patent/US12763157B2 ## CPC - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/10: Programming or data input circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/3436: {Arrangements for verifying correct programming or erasure} - G11C 2211/5621: Multilevel programming verification - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An apparatus for data storage includes circuitry and a plurality of memory cells. The memory cells are coupled to word lines (WLs), and are configured to store data values in respective predefined programming levels. The circuitry is configured to: receive data values for storage in the memory cells of a given WL, select memory cells of the given WL that are to store a given data value among the received data values, set a verification voltage for programming the selected memory cells, so that a difference between the verification voltage and a read voltage predetermined for the selected memory cells depends on a rate of drift that is expected to occur to a threshold voltage distribution associated with the selected memory cells when programmed, apply one or more programming pulses to the given WL, and verify that the selected memory cells have been programmed successfully using the set verification voltage. ## Claims ### Claim 1 An apparatus for data storage, comprising: a plurality of memory cells coupled to multiple word lines (WLs), the memory cells configured to store data values in multiple respective predefined programming levels; and storage circuitry, configured to: receive data values for storage in the memory cells of a given WL; select memory cells of the given WL that are to store a given data value among the received data values; set a verification voltage for programming the selected memory cells, so that a difference between the verification voltage and a read voltage predetermined for the selected memory cells depends on a rate of drift that is expected to occur to a threshold voltage distribution (TVD) associated with the selected memory cells when programmed, by: holding a predefined dependency between verification voltages and (i) the given data value, and (ii) one or both of a first neighbor data value previously stored in first neighbor memory cells neighboring the selected memory cells, and a second neighbor data value to be programmed in second neighbor memory cells neighboring the selected memory cells; and setting the verification voltage using the predefined dependency; apply one or more programming pulses to the given WL; and verify that the selected memory cells have been programmed successfully using the set verification voltage. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein the storage circuitry is configured to read the first neighbor memory cells using one or more read thresholds that divide a threshold voltage axis to two or more ranges, and to set the verification voltage based on the given data value and on the ranges to which the first neighbor memory cells belong. ### Claim 3 (depends on 1) The apparatus according to claim 1, wherein the storage circuitry is configured to program the selected memory cells using a coarse programming phase and a fine programming phase, and to set the verification voltage for performing the fine programming phase. ### Claim 4 (depends on 1) The apparatus according to claim 1, wherein the storage circuitry is configured to verify that the selected memory cells have been programmed successfully by using the set verification voltage for reading the selected memory cells. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein the storage circuitry is configured to verify that the selected memory cells have been programmed successfully by sensing the selected memory cells for a sensing duration that depends on the verification voltage. ### Claim 6 (depends on 1) The storage system according to claim 1, wherein the storage circuitry is configured to verify that the selected memory cells have been programmed successfully by setting a predefined bias voltage to bit lines to which the selected memory cells are coupled, so that the bias voltage depends on the verification voltage. ### Claim 7 A method for data storage, comprising: in a storage apparatus that comprises a plurality of memory cells coupled to multiple word lines (WLs), the memory cells store data values in multiple respective predefined programming levels, receiving data values for storage in the memory cells of a given WL; selecting memory cells of the given WL that are to store a given data value among the received data values; setting a verification voltage for programming the selected memory cells, so that a difference between the verification voltage and a read voltage predetermined for the selected memory cells depends on a rate of drift that is expected to occur to a threshold voltage distribution (TVD) associated with the selected memory cells when programmed, by: holding a predefined dependency between verification voltages and (i) the given data value, and (ii) one or both of a first neighbor data value previously stored in first neighbor memory cells neighboring the selected memory cells, and a second neighbor data value to be programmed in second neighbor memory cells neighboring the selected memory cells; and setting the verification voltage using the predefined dependency; applying one or more programming pulses to the given WL; and verifying that the selected memory cells have been programmed successfully using the set verification voltage. ### Claim 8 (depends on 7) The method according to claim 7, and comprising reading the first neighbor memory cells using one or more read thresholds that divide a threshold voltage axis to two or more ranges, and setting the verification voltage based on the given data value and on the ranges to which the first neighbor memory cells belong. ### Claim 9 (depends on 7) The method according to claim 7, and comprising programming the selected memory cells using a coarse programming phase and a fine programming phase, and setting the verification voltage for performing the fine programming phase. ### Claim 10 (depends on 7) The method according to claim 7, wherein verifying that the selected memory cells have been programmed successfully comprises verifying that the selected memory cells have been programmed successfully by using the set verification voltage for reading the selected memory cells. ### Claim 11 (depends on 7) The method according to claim 7, wherein verifying that the selected memory cells have been programmed successfully comprises sensing the selected memory cells for a sensing duration that depends on the verification voltage. ### Claim 12 (depends on 7) The method according to claim 7, wherein verifying that the selected memory cells have been programmed successfully comprises setting a predefined bias voltage to bit lines to which the selected memory cells are coupled, so that the bias voltage depends on the verification voltage.