Non-volatile memory with program-verify at common voltage

A method, comprising:

• performing a programming process to program a first set of non-volatile memory cells to multiple data states, each data state corresponding to a different threshold voltage distribution;
• during the programming process, performing program-verify for the first set of non-volatile memory cells being programmed including applying a same first word line voltage to the first set of non-volatile memory cells being programmed for verifying for all of the data states being verified and sensing at different sense times for different data states of the multiple data states in response to the same word line voltage;
• and
• performing an artificial intelligence inference operation including concurrently applying the same first word line voltage to the first set of non-volatile memory cells and a second set of non-volatile memory cells and sensing current from the first set of non-volatile memory cells and the second set of non-volatile memory cells by sensing current on a set of bit lines connected to the first set of non-volatile memory cells and the second set of non-volatile memory cells, each bit line of the set of bit lines is connected to one non-volatile memory cell of the first set of non-volatile memory cells and one non-volatile memory cell of the second set of non-volatile memory cells, the sensing current comprises each bit line concurrently receiving current from one non-volatile memory cell of the first set of non-volatile memory cells and one non-volatile memory cell of the second set of non-volatile memory cells in response to concurrently applying the same first word line voltage to the first set of non-volatile memory cells and to the second set of non-volatile memory cells.

A non-volatile storage apparatus, comprising:

• a first word line;
• a bit line;
• a plurality of non-volatile memory cells connected to the first word line, multiple non-volatile memory cells of the plurality of non-volatile memory cells are connected to the bit line;
• and
• a control circuit connected to the first word line and the first set of non-volatile memory cells and the bit line, the control circuit is configured to:
• apply a set of doses of programming to the first set of non-volatile memory cells connected to the first word line to program the first set of non-volatile memory cells to multiple data states, each data state corresponding to a different threshold voltage distribution,
• between doses of programming, perform program-verify for the first set of non-volatile memory cells being programmed including applying a first word line voltage to the first word line for verifying for all data states being verified and sensing at different current levels for each data state of all of the data states being verified in response to the applying the first word line voltage, and
• perform a read operation for the first set of non-volatile memory cells including concurrently sensing current from the multiple non-volatile memory cells connected to the bit line in response to applying the first word line voltage to the first word line.