# US 12,763,154 B2 · Memory device, memory system, and operating method of memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,154 B2 - Document ID: US12763154B2 - Status: Granted - Kind: B2 - Application number: 18/932,736 - Filed: 2024-10-31 - Published: 2025-03-20 - Granted: 2026-10-13 - Earliest claimed: 2023-09-19 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Tongsung Kim; Seonkyoo Lee; Younggyu Lee; Taesung Lee - Web page: https://patentgrep.com/patent/US12763154B2 ## CPC - G11C 16/32: Timing circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 29/023: {in clock generator or timing circuitry} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal from the memory controller, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously. ## Claims ### Claim 1 A memory device comprising: a first pad configured to receive a read enable signal from a memory controller; a second pad configured to receive a read duty cycle correct command signal from the memory controller; a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation; and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the second duty correction circuit comprises: a first corrector configured to correct a duty cycle of the first clock signal and the third clock signal; a second corrector configured to correct a duty cycle of the second clock signal and the fourth clock signal; and a divider configured to generate the first to fourth clock signals based on the data strobe signal. ### Claim 3 (depends on 2) The memory device of claim 2, further comprising a third pad configured to output the data strobe signal received from the first duty correction circuit to the memory controller, wherein the second duty correction circuit is configured to receive the data strobe signal from the third pad. ### Claim 4 (depends on 2) The memory device of claim 2, further comprising a switch connected between the first duty correction circuit and the second duty correction circuit, wherein the second duty correction circuit is configured to receive the data strobe signal from the first duty correction circuit when the switch is turned on. ### Claim 5 (depends on 2) The memory device of claim 2, wherein the first duty correction circuit is configured to perform the read duty cycle correct operation during a first section and a second section, and the second duty correction circuit is configured to correct a duty cycle for the first clock signal and the third clock signal in the first section and correct a duty cycle for the second clock signal and the fourth clock signal in the second section. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the first clock signal has a phase of 0°, the second clock signal has a phase of 90°, the third clock signal has a phase of 180°, and the fourth clock signal has a phase of 270°. ### Claim 7 (depends on 1) The memory device of claim 1, further comprising a plurality of dies each including the first duty correction circuit and the second duty correction circuit, wherein the second duty correction circuit included in each of the plurality of dies is configured to receive as an input a data strobe signal output from the first duty correction circuit of at least one of the plurality of dies. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the write duty cycle correct operation is a first write duty cycle correct operation, and after the read duty cycle correct operation is completed, the second duty correction circuit is configured to perform a second write duty cycle correct operation to correct a duty cycle for the first clock signal and the second clock signal which have a phase difference of 90°, in response to a write duty cycle correct command signal received from the memory controller. ### Claim 9 An operating method of a memory device, the operating method comprising: receiving a read duty cycle correct command and a read enable signal from a memory controller; when the read enable signal is received, performing a read duty cycle correct operation, based on the read duty cycle correct command, and outputting a data strobe signal, based on the read duty cycle correct operation; receiving the data strobe signal and generating first to fourth clock signals having different phases from each other based on the data strobe signal; and performing a write duty cycle correct operation to correct a duty cycle for the first to fourth clock signals, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously. ### Claim 10 (depends on 9) The operating method of claim 9, wherein the performing of the write duty cycle correct operation comprises: correcting a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180°; and correcting a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°. ### Claim 11 (depends on 9) The operating method of claim 9, wherein the first clock signal has a phase of 0°, the second clock signal has a phase of 90°, the third clock signal has a phase of 180°, and the fourth clock signal has a phase of 270°. ### Claim 12 (depends on 9) The operating method of claim 9, wherein the write duty cycle correct operation is a first write duty cycle correct operation, and the operating method further comprises, after the read duty cycle correct operation is completed, performing a second write duty cycle correct operation to correct a duty cycle for the first clock signal and the second clock signal which have a phase difference of 90°, in response to a write duty cycle correct command signal received from the memory controller. ### Claim 13 A memory system comprising: a memory controller configured to generate a read duty cycle correct command and a read enable signal; and a memory device configured to perform a training operation with respect to a read signal and a write signal, wherein the memory device comprises: a first pad configured to receive the read enable signal from the memory controller; a second pad configured to receive the read duty cycle correct command signal; a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal, based on the read duty cycle correct operation; and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first to fourth clock signals, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously. ### Claim 14 (depends on 13) The memory system of claim 13, wherein the second duty correction circuit comprises: a first corrector configured to correct a duty cycle of the first clock signal and the third clock signal; a second corrector configured to correct a duty cycle of the second clock signal and the fourth clock signal; and a divider configured to generate the first to fourth clock signals based on the data strobe signal. ### Claim 15 (depends on 13) The memory system of claim 13, further comprising a third pad configured to output the data strobe signal received from the first duty correction circuit to the memory controller, wherein the second duty correction circuit is configured to receive the data strobe signal from the third pad. ### Claim 16 (depends on 13) The memory system of claim 13, further comprising a switch connected between the first duty correction circuit and the second duty correction circuit, wherein the second duty correction circuit is configured to receive the data strobe signal from the first duty correction circuit when the switch is turned on. ### Claim 17 (depends on 13) The memory system of claim 13, wherein the first duty correction circuit is configured to perform the read duty cycle correct operation during a first section and a second section, and the second duty correction circuit is configured to correct a duty cycle for the first clock signal and the third clock signal in the first section and correct a duty cycle for the second clock signal and the fourth clock signal in the second section. ### Claim 18 (depends on 13) The memory system of claim 13, wherein the first clock signal has a phase of 0°, the second clock signal has a phase of 90°, the third clock signal has a phase of 180°, and the fourth clock signal has a phase of 270°. ### Claim 19 (depends on 13) The memory system of claim 13, further comprising a plurality of dies each including the first duty correction circuit and the second duty correction circuit, wherein the second duty correction circuit included in each of the plurality of dies is configured to receive as an input a data strobe signal output from the first duty correction circuit of at least one of the plurality of dies. ### Claim 20 (depends on 13) The memory system of claim 13, wherein the write duty cycle correct operation is a first write duty cycle correct operation, and after the read duty cycle correct operation is completed, the second duty correction circuit is configured to perform a second write duty cycle correct operation to correct a duty cycle for the first clock signal and the second clock signal which have a phase difference of 90°, in response to a write duty cycle correct command signal received from the memory controller.