Memory array and reference current circuit

An integrated circuit, comprising:

• a memory array comprising memory bit cells arranged in rows and columns, wherein a given row of the rows comprises differential reference bit cells and single-ended bit cells, the differential reference bit cells of the given row have a first input, and the single-ended bit cells of the given row have a second input;
• a set of wordline drivers, wherein a given wordline driver of the set of wordline drivers has an output coupled to the first input and to the second input;
• a control circuit comprising a row/column decoder having first control outputs, wherein each of the first control outputs are coupled to a respective wordline driver of the set of wordline drivers;
• first differential sense amplifiers, wherein outputs of a given differential reference bit cell of the differential reference bit cells are coupled to inputs of a given differential sense amplifier of the first differential sense amplifiers;
• and
• second differential sense amplifiers, wherein an output of a given single-ended bit cell of the single-ended bit cells is coupled to an amplifier input of a given differential sense amplifier of the second differential sense amplifiers.

A method of forming a circuit, comprising:

• forming a memory array comprising memory bit cells arranged in rows and columns, a given row of the rows comprises reference bit cells and single-ended bit cells, the reference bit cells are differential bit cells, and the reference bit cells comprise a first set of reference bit cells configured to store a first binary value and a second set of reference bit cells configured to store a second binary value that is different from the first binary value;
• forming a control module configured to generate a first reference current and to select the given row for a read operation;
• and
• forming an input/output module configured to compare a sensed current of a respective single-ended bit cell of the single-ended bit cells for the read operation to a second reference current, wherein the second reference current is based on the first reference current and respective currents of the first set of reference bit cells and the second set of reference bit cells.