Page buffer circuit and memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorHyungyu Yang
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array including memory cells and a page buffer circuit including page buffer units respectively connected to the memory cells through a plurality of bit lines and cache latches respectively corresponding to the page buffer units, each of the page buffer units including a main latch and a pass transistor, each connected to a corresponding sensing node, sensing nodes of at least first, second, and third page buffer units of the page buffer units connected to one another through pass transistors of the first, second, and third page buffer units, and a main latch of the first page buffer unit configured to perform a first data dump operation of transferring first data to a main latch of the second page buffer unit in a first time period of a data dump period.
Claims20
A memory device comprising:
- a memory cell array including a plurality of memory cells;
- and
- a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells through a plurality of bit lines and a plurality of cache latches respectively corresponding to the plurality of page buffer units,
- each of the plurality of page buffer units comprising a main latch and a pass transistor, each connected to a corresponding sensing node,
- sensing nodes of at least first, second, and third page buffer units of the plurality of page buffer units connected to one another through pass transistors of the first, second, and third page buffer units, and
- a main latch of the first page buffer unit configured to perform a first data dump operation of transferring first data to a main latch of the second page buffer unit in a first time period of a data dump period.
A memory device comprising:
- a first semiconductor layer including a plurality of memory cells respectively connected to a plurality of bit lines;
- and
- a second semiconductor layer above the first semiconductor layer, the second semiconductor layer including a page buffer circuit,
- the page buffer circuit comprising
- a main region including a plurality of page buffer units;
- and
- a cache region including a plurality of cache latches respectively corresponding to the plurality of page buffer units,
- each of the plurality of page buffer units comprising a main latch and a pass transistor, each connected to a corresponding sensing node,
- sensing nodes of at least first, second, and third page buffer units of the plurality of page buffer units connected to one another through pass transistors of the first, second, and third page buffer units, and
- a main latch of the first page buffer unit configured to perform a first data dump operation of transferring first data to a main latch of the second page buffer unit in a first time period of a data dump period.
A page buffer circuit comprising:
- a plurality of page buffer units;
- and
- a plurality of cache latches connected to the plurality of page buffer units through a coupling sensing node in common,
- each of the plurality of page buffer units comprising a main latch and a pass transistor, each connected to a corresponding sensing node,
- sensing nodes of at least first, second, and third page buffer units of the plurality of page buffer units connected to one another through pass transistors of the first, second, and third page buffer units, and
- a main latch of the first page buffer unit configured to perform a first data dump operation of transferring first data to a main latch of the second page buffer unit in a first time period of a data dump period.
Dependencies are inferred from the claim text.