# US 12,763,149 B2 · Logical block construction for physical blocks comprising multiple erase blocks coupled to a same string > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,149 B2 - Document ID: US12763149B2 - Status: Granted - Kind: B2 - Application number: 18/781,524 - Filed: 2024-07-23 - Published: 2025-05-01 - Granted: 2026-10-13 - Earliest claimed: 2023-10-25 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Xiangang Luo; Kishore K. Muchherla; Hong Lu; Akira Goda; Shyam Sunder Raghunathan; Peter Feeley; Emilio Camerlenghi; Paolo Tessariol - Web page: https://patentgrep.com/patent/US12763149B2 ## CPC - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block. ## Claims ### Claim 1 An apparatus, comprising: a memory array comprising a plurality of physical blocks of memory cells, wherein each physical block of the plurality comprises more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block; and a controller coupled to the memory array and configured to operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block, wherein the second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block; and wherein each physical block comprises three erase blocks, and wherein the logical block implementation includes grouping the three erase blocks from each of two physical blocks into three logical blocks with each of the three logical blocks corresponding to two different erase blocks. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the controller is configured to: track an amount of valid data on a per erase block basis; and dynamically group logical blocks based, at least partially, on the amount of valid data per erase block. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the controller is configured to provide a static grouping for the three erase blocks from each of the two physical blocks such that the two different erase blocks corresponding to each of the respective three logical blocks does not change. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the controller is configured to provide a dynamic grouping for the three erase blocks from each of the two physical blocks such that the two different erase blocks corresponding to each of the respective three logical blocks is adjustable. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein: the first erase block of a first logical block is adjacent to the first end of the particular string corresponding to the first physical block; the second erase block of the first logical block is located in the first physical block and not adjacent to the second end of the particular string corresponding to the first physical block; and the first erase block of a second logical block is adjacent to a second end of the particular string corresponding to the first physical block. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein: the first end of the particular string corresponding to the first physical block is one of a source end of the particular string and a drain end of the particular string, and the second end of the particular string corresponding to the first physical block is the other one of the source end of the particular string and the drain end of the particular string; and the second erase block of the second logical block is located within a second physical block and is adjacent to a first end of a particular string corresponding to the second physical block. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein: the first erase block of a first logical block is adjacent to the first end of the particular string corresponding to the first physical block; and the second erase block of the first logical block is located in a second physical block and adjacent to a second end of a particular string corresponding to the second physical block. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the first end of the particular string corresponding to the first physical block is a source end of the particular string, and the second end of the particular string corresponding to the first physical block is a drain end of the string, and wherein the first physical block comprises: the first erase block adjacent to the source end of the particular string; the second erase block adjacent to the drain end of the string; and at least one intermediate erase block located between the first erase block and the second erase block. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the memory array comprises replacement gate NAND memory cells. ### Claim 10 A method, comprising: forming, via a controller coupled to a memory array comprising a plurality of physical blocks of memory cells, wherein each physical block of the plurality comprises more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block, logical block groupings for the erase blocks in accordance with a particular logical block implementation; wherein forming the logical block groupings comprises grouping the erase blocks such that each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block, wherein the second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block; and performing an operation on the erase blocks based on the formed logical block groupings; wherein the method includes determining the logical block groupings such that any erase blocks that are not adjacent to either end of the particular string corresponding to the first physical block or either end of the particular string corresponding to the second physical block are adjacent to an erase block that is adjacent to either end of the particular string corresponding to the first physical block or either end of the particular string corresponding to the second physical block. ### Claim 11 (depends on 10) The method of claim 10, wherein the method includes: tracking, via the controller, an amount of valid data on an erase block basis; and dynamically adjusting, via the controller, the logical block groupings based on determined changes in the amount of valid data per erase block. ### Claim 12 (depends on 10) The method of claim 10, wherein at least some of the plurality of physical blocks comprise an even quantity of erase blocks, and wherein the particular logical block implementation comprises grouping the erase blocks such that each logical block comprises half of the erase blocks within a respective one of the at least some of the plurality of physical blocks. ### Claim 13 (depends on 10) The method of claim 10, wherein the method includes grouping the erase blocks to facilitate passage of a seed voltage to intermediate erase blocks in association with programming the intermediate erase blocks. ### Claim 14 (depends on 10) The method of claim 10, wherein forming the logical block groupings comprises forming three logical blocks out of every two physical blocks of the plurality of physical blocks. ### Claim 15 An apparatus, comprising: a memory array comprising: a first physical block of memory cells comprising at least three erase blocks each comprising memory cells coupled to a first string of memory cells corresponding to the first physical block; a second physical block of memory cells comprising at least three erase blocks each comprising memory cells coupled to a second string of memory cells corresponding to the second physical block; and a controller coupled to the memory array and configured to: determine a plurality of logical block groupings of the erase blocks of the first and second physical blocks; and perform a memory operation in accordance with the determined logical block groupings of the erase blocks; wherein the plurality of logical block groupings comprises: a first grouping comprising a first erase block adjacent to a first end of the first string and a second erase block adjacent to the first erase block; a second grouping comprising third erase block adjacent to a first end of the second string and a fourth erase block adjacent to the third erase block; and a third grouping comprising a fifth erase block adjacent to a second end of the first string and a sixth erase block adjacent to a second end of the second string. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the controller is configured to separately erase constituent erase blocks of the respective logical block groupings together. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein each of the first physical block and the second physical block comprises a number of dummy word lines separating the erase blocks within the respective physical block. ### Claim 18 An apparatus, comprising: a memory array comprising a plurality of physical blocks of memory cells, wherein each physical block of the plurality comprises more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block; and a controller coupled to the memory array and configured to operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block, wherein the second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block; wherein the first erase block of a first logical block is adjacent to the first end of the particular string corresponding to the first physical block; wherein the second erase block of the first logical block is located in the first physical block and not adjacent to the second end of the particular string corresponding to the first physical block; and wherein the first erase block of a second logical block is adjacent to a second end of the particular string corresponding to the first physical block. ### Claim 19 A method, comprising: forming, via a controller coupled to a memory array comprising a plurality of physical blocks of memory cells, wherein each physical block of the plurality comprises more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block, logical block groupings for the erase blocks in accordance with a particular logical block implementation; wherein forming the logical block groupings comprises grouping the erase blocks such that each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block, wherein the second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block; and performing an operation on the erase blocks based on the determined logical block groupings; and wherein at least some of the plurality of physical blocks comprise an even quantity of erase blocks, and wherein the particular logical block implementation comprises grouping the erase blocks such that each logical block comprises half of the erase blocks within a respective one of the at least some of the plurality of physical blocks.