# US 12,763,148 B2 · Memory device and erasing and verification method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,148 B2 - Document ID: US12763148B2 - Status: Granted - Kind: B2 - Application number: 18/765,164 - Filed: 2024-07-05 - Published: 2024-10-31 - Granted: 2026-10-13 - Earliest claimed: 2020-04-28 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Kaiwei Li; Jianquan Jia; Hongtao Liu; An Zhang - Web page: https://patentgrep.com/patent/US12763148B2 ## CPC - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a memory string and a control circuit. The memory string includes a top select gate, a memory cell, and a bottom select gate. The top select gate is coupled to a first select line, the memory cell is coupled to a word line, and the bottom select gate is coupled to a second select line. The control circuit is coupled to the first select line, the word line, and the second select line. The control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage, apply an erasing voltage to the memory string in the erasing stage, apply a first voltage to the word line in a first stage of the verification stage, apply a second voltage lower than the first voltage to the word line in a second stage after the first stage, apply a first turn-on voltage to the second select line before applying the second voltage to the word line, and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time. ## Claims ### Claim 1 A memory device, comprising: a memory string comprising a top select gate, a memory cell, and a bottom select gate, wherein the top select gate is coupled to a first select line, the memory cell is coupled to a word line, and the bottom select gate is coupled to a second select line; and a control circuit coupled to the first select line, the word line, and the second select line, wherein the control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage: apply an erasing voltage to the memory string in the erasing stage; apply a first voltage to the word line in a first stage of the verification stage; apply a second voltage to the word line in a second stage of the verification stage, the second stage being after the first stage, and the second voltage being lower than the first voltage; apply a third voltage to the word line in the second stage and after applying the second voltage to the word line, wherein the third voltage is larger than the second voltage; apply a first turn-on voltage to the second select line before applying the second voltage to the word line; and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first voltage is a pulse signal. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the application of the second voltage, the application of the first turn-on voltage, and the application of the second turn-on voltage at least partially overlap in timing sequence. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the second voltage is applied to perform verification when the top select gate and the bottom select gate are turned on. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the application of the first voltage and the application of the first turn-on voltage at least partially overlap in timing sequence. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the second voltage is equal to or lower than 0 volt. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the control circuit is further configured to: apply a fourth voltage to the word line in the erasing stage, wherein the second voltage is equal to or lower than the fourth voltage. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the control circuit is further configured to: apply the first turn-on voltage to the second select line, maintaining at least until applying the second turn-on voltage to the first select line. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the control circuit is further configured to: float the second select line before applying the first turn-on voltage to the second select line; and apply the first turn-on voltage to the second select line, starting after a floating voltage on the second select line drops. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the control circuit is further configured to apply the first turn-on voltage to the second select line, starting when the erasing voltage is applied to the memory string. ### Claim 11 A method of operating a memory device comprising a memory string, the memory string comprising a top select gate, a memory cell, and a bottom select gate, the top select gate being coupled to a first select line, the memory cell being coupled to a word line, and the bottom select gate being coupled to a second select line; the method comprising: applying an erasing voltage to the memory string in an erasing stage; applying a first voltage to the word line in a first stage of a verification stage, the verification stage being after the erasing stage; applying a second voltage to the word line in a second stage of the verification stage, the second stage being after the first stage, and the second voltage being lower than the first voltage; applying a third voltage to the word line in the second stage and after applying the second voltage to the word line, wherein the third voltage is larger than the second voltage; applying a first turn-on voltage to the second select line before applying the second voltage to the word line; and applying a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time. ### Claim 12 (depends on 11) The method of claim 11, wherein the first voltage is a pulse signal. ### Claim 13 (depends on 11) The method of claim 11, wherein the application of the second voltage, the application of the first turn-on voltage, and the application of the second turn-on voltage at least partially overlap in timing sequence. ### Claim 14 (depends on 11) The method of claim 11, wherein the application of the first voltage and the application of the first turn-on voltage at least partially overlap in timing sequence. ### Claim 15 (depends on 11) The method of claim 11, wherein the second voltage is equal to or lower than 0 volt. ### Claim 16 (depends on 11) The method of claim 11, further comprising: applying a fourth voltage to the word line in the erasing stage, wherein the second voltage is equal to or lower than the fourth voltage. ### Claim 17 (depends on 11) The method of claim 11, further comprising: applying the first turn-on voltage to the second select line, maintaining at least until applying the second turn-on voltage to the first select line. ### Claim 18 A memory system, comprising: a memory device comprising: a memory string comprising a top select gate, a memory cell, and a bottom select gate, the top select gate being coupled to a first select line, the memory cell being coupled to a word line, and the bottom select gate being coupled to a second select line; and a control circuit coupled to the first select line, the word line, and the second select line, wherein the control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage: apply an erasing voltage to the memory string in the erasing stage; apply a first voltage to the word line in a first stage of the verification stage; apply a second voltage to the word line in a second stage of the verification stage, the second stage being after the first stage, and the second voltage being lower than the first voltage; apply a third voltage to the word line in the second stage and after applying the second voltage to the word line, wherein the third voltage is larger than the second voltage; apply a first turn-on voltage to the second select line before applying the second voltage to the word line; and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time. ### Claim 19 (depends on 18) The memory system of claim 18, wherein the application of the second voltage, the application of the first turn-on voltage, and the application of the second turn-on voltage at least partially overlap in timing sequence. ### Claim 20 (depends on 18) The memory system of claim 18, wherein the second voltage is equal to or lower than 0 volt.