Nand flash memory device with a rewrite operation and operating method thereof

An operating method of a memory device including memory blocks, each of the memory blocks including a plurality of cell strings connected in parallel between a bit line and a common source line, the operating method comprising:

• programming a plurality of first ground selection transistors connected with a first ground selection line to have a first threshold voltage;
• programming a plurality of second ground selection transistors connected with a second ground selection line to have a second threshold voltage which differs from the first threshold voltage;
• based on a threshold voltage of each of at least one first ground selection transistor of the plurality of first ground selection transistors being greater than a predetermined first criterion, performing an erase operation each of on the at least one first ground selection transistor;
• and
• based on the erase operation on the at least one first ground selection transistor being completed, controlling a threshold voltage of each of the plurality of second ground selection transistors to be compared with a predetermined second criterion.

A memory device comprising:

• a plurality of memory cells respectively connected with a plurality of word lines;
• a plurality of first ground selection transistors connected with a first ground selection line and programmed to have a first threshold voltage;
• a plurality of second ground selection transistors connected with a second ground selection line and programmed to have a second threshold voltage which differs from the first threshold voltage;
• and
• a control circuit configured to, based on a voltage region of at least one transistor of the plurality of second ground selection transistors being less than a predetermined second criterion, control an erase operation to be performed on each of plurality of second ground selection transistors that includes a region which is less than the predetermined second criterion.