Word line decoder, control method of memory device and word line drive circuit

A control method of a memory device, wherein the memory device includes a plurality of cells, the method comprising:

• in an erase operation, in which one of the cells as a selected cell is selected for erase, a word line voltage coupled to a gate terminal of the selected cell is a preset negative voltage;
• in which one of the cells as a deselected cell is not selected for erase, a word line voltage coupled to a gate terminal of the deselected cell is a Hi-Z state;
• and
• not performing a refresh step of the erase operation for adjusting a threshold voltage distribution of the deselected cell.

A word line drive circuit, comprising:

• a first drive transistor, a first terminal of the first drive transistor receives a first signal, and a control terminal of the first drive transistor receives a first control signal;
• and
• a second drive transistor, a first terminal of the second drive transistor is coupled to a second terminal of the first drive transistor, a second terminal of the second drive transistor receives a revised global word line voltage, and a control terminal of the second drive transistor receives a global word line voltage,
• wherein the first terminal of the second drive transistor and the second terminal of the first drive transistor are coupled to a gate terminal of one of a plurality of cells in a memory array,
• wherein in an erase operation and the one of the plurality of cells is not selected for erase, the first control signal is enabled to enable the first drive transistor, the first signal is a Hi-Z state, and the first signal is coupled to the gate terminal of the one of the plurality of cells through the first drive transistor.