Content-addressable memory and memory control method
AssigneeRealtek Semiconductor Corp.
InventorI-Hao Chiang
Life of this patent
Estimating the term…
Abstract
A content-addressable memory includes a pre-search content-addressable memory array, a control circuit, and a main search content-addressable memory array. The pre-search content-addressable memory array is configured to perform a first data search to selectively adjust levels of a plurality of match lines in the pre-search content-addressable memory array. The control circuit is configured to generate a detection signal according to the levels of the plurality of match lines after the first data search is performed, and to generate an enable signal according to the detection signal. The main search content-addressable memory array is configured to selectively perform a second data search according to the enable signal.
Claims18
A content-addressable memory, comprising:
- a pre-search content-addressable memory array configured to perform a first data search to selectively adjust levels of a plurality of match lines in the pre-search content-addressable memory array;
- a control circuit configured to generate a detection signal according to the levels of the plurality of match lines after the first data search is performed, and to generate an enable signal according to the detection signal;
- and
- a main search content-addressable memory array configured to selectively perform a second data search according to the enable signal,
- wherein the main search content-addressable memory array comprises:
- a timing controller circuit configured to selectively generate a clock signal according to the enable signal;
- and
- a plurality of peripheral circuits configured to perform the second data search according to the clock signal.
A content-addressable memory, comprising:
- a pre-search content-addressable memory array configured to perform a first data search to selectively adjust levels of a plurality of match lines in the pre-search content-addressable memory array;
- a control circuit configured to generate a detection signal according to the levels of the plurality of match lines after the first data search is performed, and to generate an enable signal according to the detection signal;
- and
- a main search content-addressable memory array configured to selectively perform a second data search according to the enable signal,
- wherein the control circuit comprises:
- a first switch configured to be turned on according to a reset signal to transmit a voltage to a first node;
- a second switch configured to be turned on according to the level of one of the plurality of match lines;
- a third switch configured to be turned on according to the reset signal to couple the first node to ground through the second switch;
- an inverter circuit configured to generate the detection signal according to a level of the first node;
- and
- a logic gate circuit configured to generate the enable signal according to the detection signal and a control signal from a timing controller circuit.
A memory control method, comprising:
- performing, by a pre-search content-addressable memory array, a first data search to selectively adjust levels of a plurality of match lines in the pre-search content-addressable memory array;
- generating a detection signal according to the levels of the plurality of match lines after the first data search is performed, and generating an enable signal according to the detection signal;
- and
- selectively performing a second data search by a main search content-addressable memory array according to the enable signal,
- wherein the main search content-addressable memory array comprises a timing controller circuit and a plurality of peripheral circuits, and selectively performing the second data search by a main search content-addressable memory array according to the enable signal comprises:
- selectively generating, by the timing controller circuit, a clock signal according to the enable signal;
- and
- performing, by the plurality of peripheral circuits, the second data search according to the clock signal.
Dependencies are inferred from the claim text.