Semiconductor memory device including memory cells
AssigneeSamsung Electronics Co., Ltd.
InventorsJung-Hak Song, Hyun-Jin Shin, Junsuk Lee, Chanho Lee
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Abstract
A semiconductor memory device includes a first memory cell including a first variable resistor element and a first cell transistor connected to the first variable resistor element through a first source-drain electrode, a substrate having a first surface connected to the second source-drain electrode of the first cell transistor and a second surface opposing the first surface, a first bitline connected to the first source-drain electrode of the first cell transistor through the first variable resistor element, and a first source line disposed on the second surface of the substrate and connected to the second source-drain electrode.
Claims20
A semiconductor memory device comprising:
- a first memory cell comprising a first variable resistor element and a first cell transistor connected to the first variable resistor element through a first source-drain electrode;
- a substrate comprising a first surface connected to a second source-drain electrode of the first cell transistor and a second surface opposing the first surface;
- a first bitline connected to the first source-drain electrode of the first cell transistor through the first variable resistor element;
- a first source line having a first width, arranged on the second surface of the substrate and connected to the second source-drain electrode;
- and
- a second source line disposed on the first surface and electrically connected to the first source line.
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells, each comprising a variable resistor element and a cell transistor;
- a first bitline and a first source line connected to a first memory cell, among the plurality of memory cells;
- a substrate disposed between the first memory cell and the first source line, the substrate having a first surface adjacent to a first cell transistor and a second surface opposing the first surface;
- and
- a second source line disposed on the first surface and electrically connected to the first source line,
- wherein the first bitline is connected to the first cell transistor through a first variable resistor element of the first memory cell, and
- wherein the first source line is disposed on the second surface of the substrate and is connected to the first cell transistor.
A semiconductor memory device comprising:
- a first memory cell comprising a first variable resistor element and a first cell transistor connected to the first variable resistor element through a first source-drain electrode;
- a substrate comprising a first surface connected to a second source-drain electrode of the first cell transistor and a second surface opposing the first surface;
- a first bitline connected to the first source-drain electrode of the first cell transistor through the first variable resistor element;
- a first wordline disposed on the first surface to connect to a first gate electrode of the first cell transistor;
- a first additional wordline disposed on the second surface of the substrate and connected to the first gate electrode;
- a first source line disposed on the second surface and connected to the second source-drain electrode;
- and
- a second source line disposed on the first surface and electrically connected to the first source line.
Dependencies are inferred from the claim text.