Memory device and operating method thereof
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua University
InventorsWin-San Khwa, De-Qi You, Jui-Jen Wu, Meng-Fan Chang
Life of this patent
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Abstract
A method of operating a memory device is provided, including operations: generating, based on at least one weight stored in a first memory, a weight feature to be stored in a second memory different from the first memory, wherein the weight feature is associated with a number of repetitious bits, that are in neighbor positions of and the same as a most significant bit, in the at least one weight; and accessing, according to the weight feature and an address of the at least one weight, the first memory and the second memory to transmit the at least one weight to a multiply and accumulate circuit for a first neural network layer operation.
Claims20
A memory device, comprising:
- a non-volatile memory array configured to store a plurality of weights;
- a plurality of sense amplifier circuits configured to access the non-volatile memory array;
- and
- a plurality of weight read circuits coupled to the plurality of sense amplifier circuits, and each comprising:
- a weight extract circuit configured to generate a flag signal in response to a readout signal that is associated with a corresponding one weight and is generated by a corresponding sense amplifier circuit in the plurality of sense amplifier circuits;
- a memory circuit configured to store a weight feature according to the flag signal;
- and
- a weight read controller configured to control, in response to a control data and feature data associated with the weight feature, the corresponding sense amplifier circuit to output a first bit, of the corresponding one weight, as a portion of bits in the corresponding one weight.
A memory device, comprising:
- a non-volatile memory array configured to store a plurality of weights;
- a plurality of sense amplifier circuits configured to perform read operation of the plurality of weights;
- and
- a plurality of weight read circuits, and each comprising:
- a weight extract circuit configured to generate a flag signal based on a readout signal received from a corresponding sense amplifier circuit in the plurality of sense amplifier circuits;
- a memory circuit configured to store a weight feature according to the flag signal;
- and
- a weight read controller configured to selectively enable a corresponding sense amplifier circuit to output a subset of bits from a corresponding weight, based on the weight feature.
A memory device, comprising:
- a non-volatile memory array configured to store a plurality of weights;
- a plurality of sense amplifier circuits configured to access the non-volatile memory array;
- and
- a plurality of weight read circuits coupled to the plurality of sense amplifier circuits, and each comprising:
- a weight extract circuit configured to generate a flag signal in response to a readout signal that is associated with a corresponding one weight and is generated by a corresponding sense amplifier circuit in the plurality of sense amplifier circuits;
- a memory circuit configured to store a weight feature according to the flag signal;
- and
- a weight read controller configured to control, in response to a control data and feature data associated with the weight feature, the corresponding sense amplifier circuit to output a first bit, of the corresponding one weight, as a portion of bits in the corresponding one weight,
- wherein the first bit is a most significant bit in the corresponding one weight.
Dependencies are inferred from the claim text.